<ul>
              <li>Synthesizing 8051 IP core (PDF file, 50kb)</li>
              <li>Implementing 8051 IP core design on Xilinx Spartan II =
device=20
                (PDF file, 100kb)</li>
              <li>Implementing 8051 IP core design on Altera ACEX1 =
device=20
                (PDF file, 100kb)</li>
            </ul>
-->
            <DIV align=3Dright><A=20
            =
href=3D"http://www.oregano.at/ip/ip01.htm#8051_contents">Back to=20
            contents</A><BR><BR></DIV><A name=3D8051_license>
            <H3>Licensing</H3></A>
            <P><A onclick=3Djavascript:void(open_licwindow())=20
            href=3D"about:blank">The license conditions</A> may be found =
<A=20
            onclick=3Djavascript:void(open_licwindow())=20
            href=3D"about:blank">here</A>. </P>
            <DIV align=3Dright><A=20
            =
href=3D"http://www.oregano.at/ip/ip01.htm#8051_contents">Back to=20
            contents</A><BR><BR></DIV><A name=3D8051_source>
            <H3>Source Files</H3></A>
            <UL>
              <LI><A =
href=3D"http://www.oregano.at/ip/mc8051/mc8051_design.zip"=20
              target=3D_blank><IMG=20
              src=3D"http://www.oregano.at/ip/images/winzip_icon.gif" =
width=3D20=20
              border=3D0> MC8051 IP Core</A> (Zip file, 398kb) =
</LI></UL>
            <P>The VHDL source files of the IP core are provided in a <A =

            href=3D"http://www.oregano.at/ip/mc8051/mc8051_design.zip"=20
            target=3D_blank>single zip-file</A> (398 kb). The VHDL files =
naturally=20
            include a complete testbench that enables the user to verify =
the=20
            function of the MC8051 IP core and the software written. =
Beside the=20
            VHDL files we provide synthesis scripts for popular FPGA =
synthesis=20
            tools and a simple script for ASIC synthesis using =
Synopsys's=20
            DesignCompiler. </P>
            <P>Please note that there are two different kinds of version =

            identifiers used in the MC8051 project. There is the =
<I>release=20
            version ID</I> that denotes the version of the whole =
distribution=20
            (i.e. the zip-file). And there are the version identifiers =
used for=20
            every single design file generally referred to as <I>the=20
            revision</I> in the list of known bugs. </P>
            <DIV align=3Dright><A=20
            =
href=3D"http://www.oregano.at/ip/ip01.htm#8051_contents">Back to=20
            contents</A><BR><BR></DIV><A name=3D8051_comments>
            <H3>User Comments</H3></A>
            <P>Read what users say that already have used our 8051 IP =
core. </P>
            <UL>
              <LI><A href=3D"mailto:AHMursaev@mail.eltech.ru">Dr. =
Aleksander H.=20
              Mursaev</A> professor at the Saint Petersburg =
Electrotechnical=20
              University Department of Computer Science &amp; =
Engineering said=20
              <I>"... it is highly useful for my didactical work because =
it=20
              looks to be an excellent illustrative material."</I>=20
              <LI>Felix Bauer, from <A href=3D"http://www.offis.de/"=20
              target=3D_blank>OFFIS</A> about the mc8051 IP core ... =
<I>"Thanks a=20
              lot for the mc8051 source code. It is well structured and=20
              therefore easy to understand. We have mapped the core onto =
a=20
              Virtex FPGA, and it works without any complications."</I>
              <LI></LI></UL>
            <DIV align=3Dright><A=20
            =
href=3D"http://www.oregano.at/ip/ip01.htm#8051_contents">Back to=20
            contents</A><BR><BR></DIV><A name=3D8051_bugreport>
            <H3>Bug Reports</H3></A>
            <P>Although we have set huge efforts to verify the proper =
operation=20
            and compatibility of the 8051 IP core we accept that there =
still=20
            might be some bugs. We will provide you in the following a =
list of=20
            known bugs, work arounds and bug fixes. We encourage you to =
send us=20
            a detailled bug report if you find a misbehaviour of the =
8051 IP=20
            core. </P>
            <H4>List of Corrected Bugs</H4>
            <P><B>Changes with release version 1.1</B> </P>
            <LI>Register TMOD had high and low nibble swapped in file=20
            <I>mc8051_tmrctr_rtl.vhd</I>, revision 1.6 and below. This =
error has=20
            been corrected with revision 1.7.=20
            <LI>Register SCON had Bits SM0 and SM1 swapped in file=20
            <I>mc8051_siu_rtl.vhd</I>, revision 1.6 and below. This =
error has=20
            been corrected with revision 1.7.=20
            <LI>In mode 0 the serial interface unit did not output a =
clock=20
            signal when shifting in the eighth data bit in file=20
            <I>mc8051_siu_rtl.vhd</I>, revision 1.6 and below. This =
error has=20
            been corrected with revision 1.7.=20
            <P><B>Changes with release version 1.2</B> </P>
            <LI>Some XCH instructions did not work properly when using =
the=20
            internal RAM block in file <I>control_mem_rtl.vhd</I>, =
revision 1.7=20
            and below and in file <I>control_fsm_rtl.vhd</I>, revision =
1.6 and=20
            below. This problem has been corrected with revision 1.8 of =
file=20
            <I>control_mem_rtl.vhd</I> and with revision 1.7 of file=20
            <I>control_fsm_rtl.vhd</I>.=20
            <LI>The boolean instuctions ANL and ORL delivered wrong =
results=20
            under certain conditions in file <I>control_mem_rtl.vhd</I>, =

            revision 1.7 and below. This misbehavior has been corrected =
with=20
            revision 1.8 of this file.=20
            <LI>The problem with the POP SP command in file=20
            <I>control_mem_rtl.vhd</I>, revision 1.7 and below has been=20
            corrected with revision 1.8 of this file.=20
            <LI>The misbehavior with clearing the IEx-flags in file=20
            <I>control_fsm_rtl.vhd</I>, revision 1.6 and below has been=20
            corrected with revision 1.7 of this file.=20
            <P><B><IMG src=3D"http://www.oregano.at/ip/images/new.gif" =
border=3D0>=20
            Changes with release version 1.3</B> </P>
            <LI>The misbehavior during duplex operation in file=20
            <I>mc8051_siu_rtl.vhd</I>, revision 1.7 and below has been =
corrected=20
            with revision 1.8 of this file.=20
            <UL></UL>
            <DIV align=3Dright><A=20
            =
href=3D"http://www.oregano.at/ip/ip01.htm#8051_contents">Back to=20
            contents</A><BR><BR></DIV><A name=3D8051_contact>
            <H3>Contact and Support</H3></A>
            <P>If you have any comments or questions regards our 8051 IP =
core=20
            please feel free to <A =
href=3D"mailto:mc8051@oregano.at">contact=20
            us</A>. </P>
            <P>We also offer - commercial - support for using and/or =
adapting=20
            the 8051 IP core in your industrial FPGA/ASIC designs. =
Please <A=20
            href=3D"mailto:mc8051@oregano.at">contact us</A> for more =
details!=20
</P>
            <DIV align=3Dright><A=20
            =
href=3D"http://www.oregano.at/ip/ip01.htm#8051_contents">Back to=20
            =
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