#define BANK2_READ_EVENT1_BE_SET(x)              (((x) << BANK2_READ_EVENT1_BE_LSB) & BANK2_READ_EVENT1_BE_MASK)#define BANK2_READ_EVENT1_OE_MSB                 5#define BANK2_READ_EVENT1_OE_LSB                 5#define BANK2_READ_EVENT1_OE_MASK                0x00000020#define BANK2_READ_EVENT1_OE_GET(x)              (((x) & BANK2_READ_EVENT1_OE_MASK) >> BANK2_READ_EVENT1_OE_LSB)#define BANK2_READ_EVENT1_OE_SET(x)              (((x) << BANK2_READ_EVENT1_OE_LSB) & BANK2_READ_EVENT1_OE_MASK)#define BANK2_READ_EVENT1_CS_MSB                 4#define BANK2_READ_EVENT1_CS_LSB                 4#define BANK2_READ_EVENT1_CS_MASK                0x00000010#define BANK2_READ_EVENT1_CS_GET(x)              (((x) & BANK2_READ_EVENT1_CS_MASK) >> BANK2_READ_EVENT1_CS_LSB)#define BANK2_READ_EVENT1_CS_SET(x)              (((x) << BANK2_READ_EVENT1_CS_LSB) & BANK2_READ_EVENT1_CS_MASK)#define BANK2_READ_EVENT0_DC_MSB                 3#define BANK2_READ_EVENT0_DC_LSB                 3#define BANK2_READ_EVENT0_DC_MASK                0x00000008#define BANK2_READ_EVENT0_DC_GET(x)              (((x) & BANK2_READ_EVENT0_DC_MASK) >> BANK2_READ_EVENT0_DC_LSB)#define BANK2_READ_EVENT0_DC_SET(x)              (((x) << BANK2_READ_EVENT0_DC_LSB) & BANK2_READ_EVENT0_DC_MASK)#define BANK2_READ_EVENT0_BE_MSB                 2#define BANK2_READ_EVENT0_BE_LSB                 2#define BANK2_READ_EVENT0_BE_MASK                0x00000004#define BANK2_READ_EVENT0_BE_GET(x)              (((x) & BANK2_READ_EVENT0_BE_MASK) >> BANK2_READ_EVENT0_BE_LSB)#define BANK2_READ_EVENT0_BE_SET(x)              (((x) << BANK2_READ_EVENT0_BE_LSB) & BANK2_READ_EVENT0_BE_MASK)#define BANK2_READ_EVENT0_OE_MSB                 1#define BANK2_READ_EVENT0_OE_LSB                 1#define BANK2_READ_EVENT0_OE_MASK                0x00000002#define BANK2_READ_EVENT0_OE_GET(x)              (((x) & BANK2_READ_EVENT0_OE_MASK) >> BANK2_READ_EVENT0_OE_LSB)#define BANK2_READ_EVENT0_OE_SET(x)              (((x) << BANK2_READ_EVENT0_OE_LSB) & BANK2_READ_EVENT0_OE_MASK)#define BANK2_READ_EVENT0_CS_MSB                 0#define BANK2_READ_EVENT0_CS_LSB                 0#define BANK2_READ_EVENT0_CS_MASK                0x00000001#define BANK2_READ_EVENT0_CS_GET(x)              (((x) & BANK2_READ_EVENT0_CS_MASK) >> BANK2_READ_EVENT0_CS_LSB)#define BANK2_READ_EVENT0_CS_SET(x)              (((x) << BANK2_READ_EVENT0_CS_LSB) & BANK2_READ_EVENT0_CS_MASK)#define BANK2_WRITE_ADDRESS                      0x0c00402c#define BANK2_WRITE_OFFSET                       0x0000002c#define BANK2_WRITE_ENABLE_WAIT_MSB              31#define BANK2_WRITE_ENABLE_WAIT_LSB              31#define BANK2_WRITE_ENABLE_WAIT_MASK             0x80000000#define BANK2_WRITE_ENABLE_WAIT_GET(x)           (((x) & BANK2_WRITE_ENABLE_WAIT_MASK) >> BANK2_WRITE_ENABLE_WAIT_LSB)#define BANK2_WRITE_ENABLE_WAIT_SET(x)           (((x) << BANK2_WRITE_ENABLE_WAIT_LSB) & BANK2_WRITE_ENABLE_WAIT_MASK)#define BANK2_WRITE_WAIT_EVENT_MSB               30#define BANK2_WRITE_WAIT_EVENT_LSB               28#define BANK2_WRITE_WAIT_EVENT_MASK              0x70000000#define BANK2_WRITE_WAIT_EVENT_GET(x)            (((x) & BANK2_WRITE_WAIT_EVENT_MASK) >> BANK2_WRITE_WAIT_EVENT_LSB)#define BANK2_WRITE_WAIT_EVENT_SET(x)            (((x) << BANK2_WRITE_WAIT_EVENT_LSB) & BANK2_WRITE_WAIT_EVENT_MASK)#define BANK2_WRITE_END_EVENT_MSB                26#define BANK2_WRITE_END_EVENT_LSB                24#define BANK2_WRITE_END_EVENT_MASK               0x07000000#define BANK2_WRITE_END_EVENT_GET(x)             (((x) & BANK2_WRITE_END_EVENT_MASK) >> BANK2_WRITE_END_EVENT_LSB)#define BANK2_WRITE_END_EVENT_SET(x)             (((x) << BANK2_WRITE_END_EVENT_LSB) & BANK2_WRITE_END_EVENT_MASK)#define BANK2_WRITE_BURST_END_EVENT_MSB          22#define BANK2_WRITE_BURST_END_EVENT_LSB          20#define BANK2_WRITE_BURST_END_EVENT_MASK         0x00700000#define BANK2_WRITE_BURST_END_EVENT_GET(x)       (((x) & BANK2_WRITE_BURST_END_EVENT_MASK) >> BANK2_WRITE_BURST_END_EVENT_LSB)#define BANK2_WRITE_BURST_END_EVENT_SET(x)       (((x) << BANK2_WRITE_BURST_END_EVENT_LSB) & BANK2_WRITE_BURST_END_EVENT_MASK)#define BANK2_WRITE_BURST_START_EVENT_MSB        18#define BANK2_WRITE_BURST_START_EVENT_LSB        16#define BANK2_WRITE_BURST_START_EVENT_MASK       0x00070000#define BANK2_WRITE_BURST_START_EVENT_GET(x)     (((x) & BANK2_WRITE_BURST_START_EVENT_MASK) >> BANK2_WRITE_BURST_START_EVENT_LSB)#define BANK2_WRITE_BURST_START_EVENT_SET(x)     (((x) << BANK2_WRITE_BURST_START_EVENT_LSB) & BANK2_WRITE_BURST_START_EVENT_MASK)#define BANK2_WRITE_EVENT3_BE_MSB                14#define BANK2_WRITE_EVENT3_BE_LSB                14#define BANK2_WRITE_EVENT3_BE_MASK               0x00004000#define BANK2_WRITE_EVENT3_BE_GET(x)             (((x) & BANK2_WRITE_EVENT3_BE_MASK) >> BANK2_WRITE_EVENT3_BE_LSB)#define BANK2_WRITE_EVENT3_BE_SET(x)             (((x) << BANK2_WRITE_EVENT3_BE_LSB) & BANK2_WRITE_EVENT3_BE_MASK)#define BANK2_WRITE_EVENT3_WE_MSB                13#define BANK2_WRITE_EVENT3_WE_LSB                13#define BANK2_WRITE_EVENT3_WE_MASK               0x00002000#define BANK2_WRITE_EVENT3_WE_GET(x)             (((x) & BANK2_WRITE_EVENT3_WE_MASK) >> BANK2_WRITE_EVENT3_WE_LSB)#define BANK2_WRITE_EVENT3_WE_SET(x)             (((x) << BANK2_WRITE_EVENT3_WE_LSB) & BANK2_WRITE_EVENT3_WE_MASK)#define BANK2_WRITE_EVENT3_CS_MSB                12#define BANK2_WRITE_EVENT3_CS_LSB                12#define BANK2_WRITE_EVENT3_CS_MASK               0x00001000#define BANK2_WRITE_EVENT3_CS_GET(x)             (((x) & BANK2_WRITE_EVENT3_CS_MASK) >> BANK2_WRITE_EVENT3_CS_LSB)#define BANK2_WRITE_EVENT3_CS_SET(x)             (((x) << BANK2_WRITE_EVENT3_CS_LSB) & BANK2_WRITE_EVENT3_CS_MASK)#define BANK2_WRITE_EVENT2_BE_MSB                10#define BANK2_WRITE_EVENT2_BE_LSB                10#define BANK2_WRITE_EVENT2_BE_MASK               0x00000400#define BANK2_WRITE_EVENT2_BE_GET(x)             (((x) & BANK2_WRITE_EVENT2_BE_MASK) >> BANK2_WRITE_EVENT2_BE_LSB)#define BANK2_WRITE_EVENT2_BE_SET(x)             (((x) << BANK2_WRITE_EVENT2_BE_LSB) & BANK2_WRITE_EVENT2_BE_MASK)#define BANK2_WRITE_EVENT2_WE_MSB                9#define BANK2_WRITE_EVENT2_WE_LSB                9#define BANK2_WRITE_EVENT2_WE_MASK               0x00000200#define BANK2_WRITE_EVENT2_WE_GET(x)             (((x) & BANK2_WRITE_EVENT2_WE_MASK) >> BANK2_WRITE_EVENT2_WE_LSB)#define BANK2_WRITE_EVENT2_WE_SET(x)             (((x) << BANK2_WRITE_EVENT2_WE_LSB) & BANK2_WRITE_EVENT2_WE_MASK)#define BANK2_WRITE_EVENT2_CS_MSB                8#define BANK2_WRITE_EVENT2_CS_LSB                8#define BANK2_WRITE_EVENT2_CS_MASK               0x00000100#define BANK2_WRITE_EVENT2_CS_GET(x)             (((x) & BANK2_WRITE_EVENT2_CS_MASK) >> BANK2_WRITE_EVENT2_CS_LSB)#define BANK2_WRITE_EVENT2_CS_SET(x)             (((x) << BANK2_WRITE_EVENT2_CS_LSB) & BANK2_WRITE_EVENT2_CS_MASK)#define BANK2_WRITE_EVENT1_BE_MSB                6#define BANK2_WRITE_EVENT1_BE_LSB                6#define BANK2_WRITE_EVENT1_BE_MASK               0x00000040#define BANK2_WRITE_EVENT1_BE_GET(x)             (((x) & BANK2_WRITE_EVENT1_BE_MASK) >> BANK2_WRITE_EVENT1_BE_LSB)#define BANK2_WRITE_EVENT1_BE_SET(x)             (((x) << BANK2_WRITE_EVENT1_BE_LSB) & BANK2_WRITE_EVENT1_BE_MASK)#define BANK2_WRITE_EVENT1_WE_MSB                5#define BANK2_WRITE_EVENT1_WE_LSB                5#define BANK2_WRITE_EVENT1_WE_MASK               0x00000020#define BANK2_WRITE_EVENT1_WE_GET(x)             (((x) & BANK2_WRITE_EVENT1_WE_MASK) >> BANK2_WRITE_EVENT1_WE_LSB)#define BANK2_WRITE_EVENT1_WE_SET(x)             (((x) << BANK2_WRITE_EVENT1_WE_LSB) & BANK2_WRITE_EVENT1_WE_MASK)#define BANK2_WRITE_EVENT1_CS_MSB                4#define BANK2_WRITE_EVENT1_CS_LSB                4#define BANK2_WRITE_EVENT1_CS_MASK               0x00000010#define BANK2_WRITE_EVENT1_CS_GET(x)             (((x) & BANK2_WRITE_EVENT1_CS_MASK) >> BANK2_WRITE_EVENT1_CS_LSB)#define BANK2_WRITE_EVENT1_CS_SET(x)             (((x) << BANK2_WRITE_EVENT1_CS_LSB) & BANK2_WRITE_EVENT1_CS_MASK)#define BANK2_WRITE_EVENT0_BE_MSB                2#define BANK2_WRITE_EVENT0_BE_LSB                2#define BANK2_WRITE_EVENT0_BE_MASK               0x00000004#define BANK2_WRITE_EVENT0_BE_GET(x)             (((x) & BANK2_WRITE_EVENT0_BE_MASK) >> BANK2_WRITE_EVENT0_BE_LSB)#define BANK2_WRITE_EVENT0_BE_SET(x)             (((x) << BANK2_WRITE_EVENT0_BE_LSB) & BANK2_WRITE_EVENT0_BE_MASK)#define BANK2_WRITE_EVENT0_WE_MSB                1#define BANK2_WRITE_EVENT0_WE_LSB                1#define BANK2_WRITE_EVENT0_WE_MASK               0x00000002#define BANK2_WRITE_EVENT0_WE_GET(x)             (((x) & BANK2_WRITE_EVENT0_WE_MASK) >> BANK2_WRITE_EVENT0_WE_LSB)#define BANK2_WRITE_EVENT0_WE_SET(x)             (((x) << BANK2_WRITE_EVENT0_WE_LSB) & BANK2_WRITE_EVENT0_WE_MASK)#define BANK2_WRITE_EVENT0_CS_MSB                0#define BANK2_WRITE_EVENT0_CS_LSB                0#define BANK2_WRITE_EVENT0_CS_MASK               0x00000001#define BANK2_WRITE_EVENT0_CS_GET(x)             (((x) & BANK2_WRITE_EVENT0_CS_MASK) >> BANK2_WRITE_EVENT0_CS_LSB)#define BANK2_WRITE_EVENT0_CS_SET(x)             (((x) << BANK2_WRITE_EVENT0_CS_LSB) & BANK2_WRITE_EVENT0_CS_MASK)#define MC_REMAP_VALID_ADDRESS                   0x0c004080#define MC_REMAP_VALID_OFFSET                    0x00000080#define MC_REMAP_VALID_BIT_MSB                   0#define MC_REMAP_VALID_BIT_LSB                   0#define MC_REMAP_VALID_BIT_MASK                  0x00000001#define MC_REMAP_VALID_BIT_GET(x)                (((x) & MC_REMAP_VALID_BIT_MASK) >> MC_REMAP_VALID_BIT_LSB)#define MC_REMAP_VALID_BIT_SET(x)                (((x) << MC_REMAP_VALID_BIT_LSB) & MC_REMAP_VALID_BIT_MASK)#define MC_REMAP_SIZE_ADDRESS                    0x0c004100#define MC_REMAP_SIZE_OFFSET                     0x00000100#define MC_REMAP_SIZE_VALUE_MSB                  2#define MC_REMAP_SIZE_VALUE_LSB                  0#define MC_REMAP_SIZE_VALUE_MASK                 0x00000007#define MC_REMAP_SIZE_VALUE_GET(x)               (((x) & MC_REMAP_SIZE_VALUE_MASK) >> MC_REMAP_SIZE_VALUE_LSB)#define MC_REMAP_SIZE_VALUE_SET(x)               (((x) << MC_REMAP_SIZE_VALUE_LSB) & MC_REMAP_SIZE_VALUE_MASK)#define MC_REMAP_COMPARE_ADDRESS                 0x0c004180#define MC_REMAP_COMPARE_OFFSET                  0x00000180#define MC_REMAP_COMPARE_ADDRESS_MSB             17#define MC_REMAP_COMPARE_ADDRESS_LSB             4#define MC_REMAP_COMPARE_ADDRESS_MASK            0x0003fff0#define MC_REMAP_COMPARE_ADDRESS_GET(x)          (((x) & MC_REMAP_COMPARE_ADDRESS_MASK) >> MC_REMAP_COMPARE_ADDRESS_LSB)#define MC_REMAP_COMPARE_ADDRESS_SET(x)          (((x) << MC_REMAP_COMPARE_ADDRESS_LSB) & MC_REMAP_COMPARE_ADDRESS_MASK)#define MC_REMAP_TARGET_ADDRESS                  0x0c004200#define MC_REMAP_TARGET_OFFSET                   0x00000200#define MC_REMAP_TARGET_ADDRESS_MSB              16#define MC_REMAP_TARGET_ADDRESS_LSB              4#define MC_REMAP_TARGET_ADDRESS_MASK             0x0001fff0#define MC_REMAP_TARGET_ADDRESS_GET(x)           (((x) & MC_REMAP_TARGET_ADDRESS_MASK) >> MC_REMAP_TARGET_ADDRESS_LSB)#define MC_REMAP_TARGET_ADDRESS_SET(x)           (((x) << MC_REMAP_TARGET_ADDRESS_LSB) & MC_REMAP_TARGET_ADDRESS_MASK)#define G729_ROM_ADDRESS                         0x0c004280#define G729_ROM_OFFSET                          0x00000280#define G729_ROM_ENABLE_MSB                      0#define G729_ROM_ENABLE_LSB                      0#define G729_ROM_ENABLE_MASK                     0x00000001#define G729_ROM_ENABLE_GET(x)                   (((x) & G729_ROM_ENABLE_MASK) >> G729_ROM_ENABLE_LSB)#define G729_ROM_ENABLE_SET(x)                   (((x) << G729_ROM_ENABLE_LSB) & G729_ROM_ENABLE_MASK)#define ERROR_VALID_ADDRESS                      0x0c004284#define ERROR_VALID_OFFSET                       0x00000284#define ERROR_VALID_ERROR_CAPTURE_ENABLE_MSB     8#define ERROR_VALID_ERROR_CAPTURE_ENABLE_LSB     8#define ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK    0x00000100#define ERROR_VALID_ERROR_CAPTURE_ENABLE_GET(x)  (((x) & ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK) >> ERROR_VALID_ERROR_CAPTURE_ENABLE_LSB)#define ERROR_VALID_ERROR_CAPTURE_ENABLE_SET(x)  (((x) << ERROR_VALID_ERROR_CAPTURE_ENABLE_LSB) & ERROR_VALID_ERROR_CAPTURE_ENABLE_MASK)#define ERROR_VALID_APB_ERROR_OVERFLOW_MSB       5#define ERROR_VALID_APB_ERROR_OVERFLOW_LSB       5#define ERROR_VALID_APB_ERROR_OVERFLOW_MASK      0x00000020#define ERROR_VALID_APB_ERROR_OVERFLOW_GET(x)    (((x) & ERROR_VALID_APB_ERROR_OVERFLOW_MASK) >> ERROR_VALID_APB_ERROR_OVERFLOW_LSB)#define ERROR_VALID_APB_ERROR_OVERFLOW_SET(x)    (((x) << ERROR_VALID_APB_ERROR_OVERFLOW_LSB) & ERROR_VALID_APB_ERROR_OVERFLOW_MASK)#d