/* * Copyright 2006 Atheros Communications, Inc. * *  Wireless Network driver for Atheros AR6001 * *  This program is free software; you can redistribute it and/or modify *  it under the terms of the GNU General Public License version 2 as *  published by the Free Software Foundation; * *  Software distributed under the License is distributed on an "AS *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or *  implied. See the License for the specific language governing *  rights and limitations under the License. * * */#ifndef _MBOX_REG_H_#define _MBOX_REG_H_#define MBOX_FIFO_ADDRESS                        0x0c014000#define MBOX_FIFO_OFFSET                         0x00000000#define MBOX_FIFO_DATA_MSB                       19#define MBOX_FIFO_DATA_LSB                       0#define MBOX_FIFO_DATA_MASK                      0x000fffff#define MBOX_FIFO_DATA_GET(x)                    (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)#define MBOX_FIFO_DATA_SET(x)                    (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)#define MBOX_FIFO_STATUS_ADDRESS                 0x0c014010#define MBOX_FIFO_STATUS_OFFSET                  0x00000010#define MBOX_FIFO_STATUS_EMPTY_MSB               19#define MBOX_FIFO_STATUS_EMPTY_LSB               16#define MBOX_FIFO_STATUS_EMPTY_MASK              0x000f0000#define MBOX_FIFO_STATUS_EMPTY_GET(x)            (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)#define MBOX_FIFO_STATUS_EMPTY_SET(x)            (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)#define MBOX_FIFO_STATUS_FULL_MSB                15#define MBOX_FIFO_STATUS_FULL_LSB                12#define MBOX_FIFO_STATUS_FULL_MASK               0x0000f000#define MBOX_FIFO_STATUS_FULL_GET(x)             (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)#define MBOX_FIFO_STATUS_FULL_SET(x)             (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)#define MBOX_DMA_POLICY_ADDRESS                  0x0c014014#define MBOX_DMA_POLICY_OFFSET                   0x00000014#define MBOX_DMA_POLICY_TX_QUANTUM_MSB           3#define MBOX_DMA_POLICY_TX_QUANTUM_LSB           3#define MBOX_DMA_POLICY_TX_QUANTUM_MASK          0x00000008#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)#define MBOX_DMA_POLICY_TX_ORDER_MSB             2#define MBOX_DMA_POLICY_TX_ORDER_LSB             2#define MBOX_DMA_POLICY_TX_ORDER_MASK            0x00000004#define MBOX_DMA_POLICY_TX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)#define MBOX_DMA_POLICY_TX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)#define MBOX_DMA_POLICY_RX_QUANTUM_MSB           1#define MBOX_DMA_POLICY_RX_QUANTUM_LSB           1#define MBOX_DMA_POLICY_RX_QUANTUM_MASK          0x00000002#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x)        (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x)        (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)#define MBOX_DMA_POLICY_RX_ORDER_MSB             0#define MBOX_DMA_POLICY_RX_ORDER_LSB             0#define MBOX_DMA_POLICY_RX_ORDER_MASK            0x00000001#define MBOX_DMA_POLICY_RX_ORDER_GET(x)          (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)#define MBOX_DMA_POLICY_RX_ORDER_SET(x)          (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x0c014018#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000018#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)#define MBOX0_DMA_RX_CONTROL_ADDRESS             0x0c01401c#define MBOX0_DMA_RX_CONTROL_OFFSET              0x0000001c#define MBOX0_DMA_RX_CONTROL_RESUME_MSB          2#define MBOX0_DMA_RX_CONTROL_RESUME_LSB          2#define MBOX0_DMA_RX_CONTROL_RESUME_MASK         0x00000004#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)#define MBOX0_DMA_RX_CONTROL_START_MSB           1#define MBOX0_DMA_RX_CONTROL_START_LSB           1#define MBOX0_DMA_RX_CONTROL_START_MASK          0x00000002#define MBOX0_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)#define MBOX0_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)#define MBOX0_DMA_RX_CONTROL_STOP_MSB            0#define MBOX0_DMA_RX_CONTROL_STOP_LSB            0#define MBOX0_DMA_RX_CONTROL_STOP_MASK           0x00000001#define MBOX0_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)#define MBOX0_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x0c014020#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000020#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)#define MBOX0_DMA_TX_CONTROL_ADDRESS             0x0c014024#define MBOX0_DMA_TX_CONTROL_OFFSET              0x00000024#define MBOX0_DMA_TX_CONTROL_RESUME_MSB          2#define MBOX0_DMA_TX_CONTROL_RESUME_LSB          2#define MBOX0_DMA_TX_CONTROL_RESUME_MASK         0x00000004#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)#define MBOX0_DMA_TX_CONTROL_START_MSB           1#define MBOX0_DMA_TX_CONTROL_START_LSB           1#define MBOX0_DMA_TX_CONTROL_START_MASK          0x00000002#define MBOX0_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)#define MBOX0_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)#define MBOX0_DMA_TX_CONTROL_STOP_MSB            0#define MBOX0_DMA_TX_CONTROL_STOP_LSB            0#define MBOX0_DMA_TX_CONTROL_STOP_MASK           0x00000001#define MBOX0_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)#define MBOX0_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x0c014028#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000028#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)#define MBOX1_DMA_RX_CONTROL_ADDRESS             0x0c01402c#define MBOX1_DMA_RX_CONTROL_OFFSET              0x0000002c#define MBOX1_DMA_RX_CONTROL_RESUME_MSB          2#define MBOX1_DMA_RX_CONTROL_RESUME_LSB          2#define MBOX1_DMA_RX_CONTROL_RESUME_MASK         0x00000004#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)#define MBOX1_DMA_RX_CONTROL_START_MSB           1#define MBOX1_DMA_RX_CONTROL_START_LSB           1#define MBOX1_DMA_RX_CONTROL_START_MASK          0x00000002#define MBOX1_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)#define MBOX1_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)#define MBOX1_DMA_RX_CONTROL_STOP_MSB            0#define MBOX1_DMA_RX_CONTROL_STOP_LSB            0#define MBOX1_DMA_RX_CONTROL_STOP_MASK           0x00000001#define MBOX1_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)#define MBOX1_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x0c014030#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000030#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)#define MBOX1_DMA_TX_CONTROL_ADDRESS             0x0c014034#define MBOX1_DMA_TX_CONTROL_OFFSET              0x00000034#define MBOX1_DMA_TX_CONTROL_RESUME_MSB          2#define MBOX1_DMA_TX_CONTROL_RESUME_LSB          2#define MBOX1_DMA_TX_CONTROL_RESUME_MASK         0x00000004#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)#define MBOX1_DMA_TX_CONTROL_START_MSB           1#define MBOX1_DMA_TX_CONTROL_START_LSB           1#define MBOX1_DMA_TX_CONTROL_START_MASK          0x00000002#define MBOX1_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)#define MBOX1_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)#define MBOX1_DMA_TX_CONTROL_STOP_MSB            0#define MBOX1_DMA_TX_CONTROL_STOP_LSB            0#define MBOX1_DMA_TX_CONTROL_STOP_MASK           0x00000001#define MBOX1_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)#define MBOX1_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x0c014038#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000038#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)#define MBOX2_DMA_RX_CONTROL_ADDRESS             0x0c01403c#define MBOX2_DMA_RX_CONTROL_OFFSET              0x0000003c#define MBOX2_DMA_RX_CONTROL_RESUME_MSB          2#define MBOX2_DMA_RX_CONTROL_RESUME_LSB          2#define MBOX2_DMA_RX_CONTROL_RESUME_MASK         0x00000004#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)#define MBOX2_DMA_RX_CONTROL_START_MSB           1#define MBOX2_DMA_RX_CONTROL_START_LSB           1