#define MBOX2_DMA_RX_CONTROL_START_MASK          0x00000002#define MBOX2_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)#define MBOX2_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)#define MBOX2_DMA_RX_CONTROL_STOP_MSB            0#define MBOX2_DMA_RX_CONTROL_STOP_LSB            0#define MBOX2_DMA_RX_CONTROL_STOP_MASK           0x00000001#define MBOX2_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)#define MBOX2_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x0c014040#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000040#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)#define MBOX2_DMA_TX_CONTROL_ADDRESS             0x0c014044#define MBOX2_DMA_TX_CONTROL_OFFSET              0x00000044#define MBOX2_DMA_TX_CONTROL_RESUME_MSB          2#define MBOX2_DMA_TX_CONTROL_RESUME_LSB          2#define MBOX2_DMA_TX_CONTROL_RESUME_MASK         0x00000004#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)#define MBOX2_DMA_TX_CONTROL_START_MSB           1#define MBOX2_DMA_TX_CONTROL_START_LSB           1#define MBOX2_DMA_TX_CONTROL_START_MASK          0x00000002#define MBOX2_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)#define MBOX2_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)#define MBOX2_DMA_TX_CONTROL_STOP_MSB            0#define MBOX2_DMA_TX_CONTROL_STOP_LSB            0#define MBOX2_DMA_TX_CONTROL_STOP_MASK           0x00000001#define MBOX2_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)#define MBOX2_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS     0x0c014048#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET      0x00000048#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)#define MBOX3_DMA_RX_CONTROL_ADDRESS             0x0c01404c#define MBOX3_DMA_RX_CONTROL_OFFSET              0x0000004c#define MBOX3_DMA_RX_CONTROL_RESUME_MSB          2#define MBOX3_DMA_RX_CONTROL_RESUME_LSB          2#define MBOX3_DMA_RX_CONTROL_RESUME_MASK         0x00000004#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)#define MBOX3_DMA_RX_CONTROL_START_MSB           1#define MBOX3_DMA_RX_CONTROL_START_LSB           1#define MBOX3_DMA_RX_CONTROL_START_MASK          0x00000002#define MBOX3_DMA_RX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)#define MBOX3_DMA_RX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)#define MBOX3_DMA_RX_CONTROL_STOP_MSB            0#define MBOX3_DMA_RX_CONTROL_STOP_LSB            0#define MBOX3_DMA_RX_CONTROL_STOP_MASK           0x00000001#define MBOX3_DMA_RX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)#define MBOX3_DMA_RX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS     0x0c014050#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET      0x00000050#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)#define MBOX3_DMA_TX_CONTROL_ADDRESS             0x0c014054#define MBOX3_DMA_TX_CONTROL_OFFSET              0x00000054#define MBOX3_DMA_TX_CONTROL_RESUME_MSB          2#define MBOX3_DMA_TX_CONTROL_RESUME_LSB          2#define MBOX3_DMA_TX_CONTROL_RESUME_MASK         0x00000004#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x)       (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x)       (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)#define MBOX3_DMA_TX_CONTROL_START_MSB           1#define MBOX3_DMA_TX_CONTROL_START_LSB           1#define MBOX3_DMA_TX_CONTROL_START_MASK          0x00000002#define MBOX3_DMA_TX_CONTROL_START_GET(x)        (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)#define MBOX3_DMA_TX_CONTROL_START_SET(x)        (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)#define MBOX3_DMA_TX_CONTROL_STOP_MSB            0#define MBOX3_DMA_TX_CONTROL_STOP_LSB            0#define MBOX3_DMA_TX_CONTROL_STOP_MASK           0x00000001#define MBOX3_DMA_TX_CONTROL_STOP_GET(x)         (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)#define MBOX3_DMA_TX_CONTROL_STOP_SET(x)         (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)#define MBOX_INT_STATUS_ADDRESS                  0x0c014058#define MBOX_INT_STATUS_OFFSET                   0x00000058#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB      31#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB      28#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK     0xf0000000#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB  27#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB  24#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB      23#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB      20#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK     0x00f00000#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)#define MBOX_INT_STATUS_TX_OVERFLOW_MSB          17#define MBOX_INT_STATUS_TX_OVERFLOW_LSB          17#define MBOX_INT_STATUS_TX_OVERFLOW_MASK         0x00020000#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB         16#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB         16#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK        0x00010000#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB         15#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB         12#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK        0x0000f000#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)#define MBOX_INT_STATUS_RX_NOT_FULL_MSB          11#define MBOX_INT_STATUS_RX_NOT_FULL_LSB          8#define MBOX_INT_STATUS_RX_NOT_FULL_MASK         0x00000f00#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)#define MBOX_INT_STATUS_HOST_MSB                 7#define MBOX_INT_STATUS_HOST_LSB                 0#define MBOX_INT_STATUS_HOST_MASK                0x000000ff#define MBOX_INT_STATUS_HOST_GET(x)              (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)#define MBOX_INT_STATUS_HOST_SET(x)              (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)#define MBOX_INT_ENABLE_ADDRESS                  0x0c01405c#define MBOX_INT_ENABLE_OFFSET                   0x0000005c#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB      31#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB      28#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK     0xf0000000#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB  27#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB  24#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB      23#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB      20#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK     0x00f00000#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)   (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)   (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB          17#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB          17#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK         0x00020000#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)       (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)       (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB         16#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB         16#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK        0x00010000#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)      (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)      (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB         15#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB         12#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK        0x0000f000#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)      (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)      (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB          11#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB          8#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK         0x00000f00#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)       (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)       (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)#define MBOX_INT_ENABLE_HOST_MSB                 7#define MBOX_INT_ENABLE_HOST_LSB                 0#define MBOX_INT_ENABLE_HOST_MASK                0x000000ff#define MBOX_INT_ENABLE_HOST_GET(x)              (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)#define MBOX_INT_ENABLE_HOST_SET(x)              (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)#define INT_HOST_ADDRESS                         0x0c014060#define INT_HOST_OFFSET                          0x00000060#define INT_HOST_VECTOR_MSB                      7#define INT_HOST_VECTOR_LSB                      0#define INT_HOST_VECTOR_MASK                     0x000000ff#define INT_HOST_VECTOR_GET(x)                   (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)#define INT_HOST_VECTOR_SET(x)                   (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)#define LOCAL_COUNT_ADDRESS                      0x0c014080#define LOCAL_COUNT_OFFSET                       0x00000080#define LOCAL_COUNT_VALUE_MSB                    7