// Write register settings
    //DisableInterrupts;
    halSpiWriteReg(CCxxx0_FSCTRL1,  rfSettings.FSCTRL1);
    halSpiWriteReg(CCxxx0_FSCTRL0,  rfSettings.FSCTRL0);
    halSpiWriteReg(CCxxx0_FREQ2,    rfSettings.FREQ2);
    halSpiWriteReg(CCxxx0_FREQ1,    rfSettings.FREQ1);
    halSpiWriteReg(CCxxx0_FREQ0,    rfSettings.FREQ0);
    halSpiWriteReg(CCxxx0_MDMCFG4,  rfSettings.MDMCFG4);
    halSpiWriteReg(CCxxx0_MDMCFG3,  rfSettings.MDMCFG3);
    halSpiWriteReg(CCxxx0_MDMCFG2,  rfSettings.MDMCFG2);
    halSpiWriteReg(CCxxx0_MDMCFG1,  rfSettings.MDMCFG1);
    halSpiWriteReg(CCxxx0_MDMCFG0,  rfSettings.MDMCFG0);
    halSpiWriteReg(CCxxx0_CHANNR,   rfSettings.CHANNR);
    halSpiWriteReg(CCxxx0_DEVIATN,  rfSettings.DEVIATN);
    halSpiWriteReg(CCxxx0_FREND1,   rfSettings.FREND1);
    halSpiWriteReg(CCxxx0_FREND0,   rfSettings.FREND0);
    halSpiWriteReg(CCxxx0_MCSM0 ,   rfSettings.MCSM0 );
    halSpiWriteReg(CCxxx0_FOCCFG,   rfSettings.FOCCFG);
    halSpiWriteReg(CCxxx0_BSCFG,    rfSettings.BSCFG);
    halSpiWriteReg(CCxxx0_AGCCTRL2, rfSettings.AGCCTRL2);
    halSpiWriteReg(CCxxx0_AGCCTRL0, rfSettings.AGCCTRL0);
    halSpiWriteReg(CCxxx0_FSCAL3,   rfSettings.FSCAL3);
    halSpiWriteReg(CCxxx0_FSCAL2,   rfSettings.FSCAL2);
    halSpiWriteReg(CCxxx0_FSCAL0,   rfSettings.FSCAL0);
    halSpiWriteReg(CCxxx0_FSTEST,   rfSettings.FSTEST);
    halSpiWriteReg(CCxxx0_TEST2,    rfSettings.TEST2);
    halSpiWriteReg(CCxxx0_TEST1,    rfSettings.TEST1);
    halSpiWriteReg(CCxxx0_TEST0,    rfSettings.TEST0);
    halSpiWriteReg(CCxxx0_IOCFG2,   rfSettings.IOCFG2);
    halSpiWriteReg(CCxxx0_IOCFG0,   rfSettings.IOCFG0);
    halSpiWriteReg(CCxxx0_PKTCTRL1, rfSettings.PKTCTRL1);
    halSpiWriteReg(CCxxx0_PKTCTRL0, rfSettings.PKTCTRL0);
    halSpiWriteReg(CCxxx0_ADDR,     rfSettings.ADDR);
    halSpiWriteReg(CCxxx0_PKTLEN,   rfSettings.PKTLEN);
    //EnableInterrupts;
}// halRfWriteRfSettings
//-------------------------------------------------------------------------------------------------------
//  BYTE halSpiReadReg(BYTE addr)
//
//  DESCRIPTION:
//      This function gets the value of a single specified CCxxx0 register.
//
//  ARGUMENTS:
//      BYTE addr
//          Address of the CCxxx0 register to be accessed.
//
//  RETURN VALUE:
//      BYTE
//          Value of the accessed CCxxx0 register.
//-------------------------------------------------------------------------------------------------------
BYTE halSpiReadReg(BYTE addr) {
    BYTE x;
   // SPI0CFG   = 0x40;       //CKPHA=0  CKPOL=0
    CC2500_NCS = 0;
    while (CC2500_MISO)
    {
    	 ;//__RESET_WATCHDOG();
    }
    SPI0DAT = (addr | READ_SINGLE);
    SPI_WAIT();
    //SPI0DAT = 0;
    //SPI_WAIT();
    x =SPIGet();
    CC2500_NCS = 1;
  //  SPI0CFG   = 0x70;       //CKPHA=1  CKPOL=1
    return x;
}// halSpiReadReg
//-------------------------------------------------------------------------------------------------------
//  void halSpiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count)
//
//  DESCRIPTION:
//      This function writes to multiple CCxxx0 register, using SPI burst access.
//
//  ARGUMENTS:
//      BYTE addr
//          Address of the first CCxxx0 register to be accessed.
//      BYTE *buffer
//          Array of bytes to be written into a corresponding range of
//          CCxx00 registers, starting by the address specified in _addr_.
//      BYTE count
//          Number of bytes to be written to the subsequent CCxxx0 registers.
//-------------------------------------------------------------------------------------------------------
void halSpiWriteBurstReg(BYTE addr,BYTE * buffer, BYTE count) {
    unsigned char i;
    //SPI0CFG   = 0x40;       //CKPHA=0  CKPOL=0

    CC2500_NCS = 0;

    while (CC2500_MISO)
    {
    	;//__RESET_WATCHDOG();

    }
    SPI0DAT = addr | WRITE_BURST;
    SPI_WAIT();
    for (i = 0; i < count; i++) {
        SPI0DAT = buffer[i];
        SPI_WAIT();
    }
    CC2500_NCS = 1;
//    SPI0CFG   = 0x70;       //CKPHA=1  CKPOL=1
}// halSpiWriteBurstReg

//-------------------------------------------------------------------------------------------------------
//  void halSpiStrobe(BYTE strobe)
//
//  DESCRIPTION:
//      Function for writing a strobe command to the CCxxx0
//
//  ARGUMENTS:
//      BYTE strobe
//          Strobe command
//-------------------------------------------------------------------------------------------------------
void halSpiStrobe(BYTE strobe) {
   // SPI0CFG   = 0x40;       //CKPHA=0  CKPOL=0
    CC2500_NCS = 0;
    while (CC2500_MISO)
    {
    	; //__RESET_WATCHDOG();
    }

    //------------------------------------
    /*while (GDO0_PIN)
    {
    	 __RESET_WATCHDOG();
    }*/
    SPI0DAT = strobe;
    SPI_WAIT();
    CC2500_NCS = 1;
    //halWait(20);
  //  SPI0CFG   = 0x70;       //CKPHA=1  CKPOL=1
}// halSpiStrobe

//-------------------------------------------------------------------------------------------------------
//  void halRfSendPacket(BYTE *txBuffer, UINT8 size)
//
//  DESCRIPTION:
//      This function can be used to transmit a packet with packet length up to 63 bytes.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and
//      de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.
//
//  ARGUMENTS:
//      BYTE *txBuffer
//          Pointer to a buffer containing the data that are going to be transmitted
//
//      UINT8 size
//          The size of the txBuffer
//-------------------------------------------------------------------------------------------------------
void halRfSendPacket(unsigned char *txBuffer,unsigned char size) {

    halSpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);

    halSpiStrobe(CCxxx0_STX);
}// halRfSendPacket

//-------------------------------------------------------------------------------------------------------
//  BYTE halSpiReadStatus(BYTE addr)
//
//  DESCRIPTION:
//      This function reads a CCxxx0 status register.
//
//  ARGUMENTS:
//      BYTE addr
//          Address of the CCxxx0 status register to be accessed.
//
//  RETURN VALUE:
//      BYTE
//          Value of the accessed CCxxx0 status register.
//-------------------------------------------------------------------------------------------------------
BYTE halSpiReadStatus(BYTE addr) {
    BYTE x;
  //  SPI0CFG   = 0x40;       //CKPHA=0  CKPOL=0
    CC2500_NCS = 0;
    while (CC2500_MISO)
    {
    	; //__RESET_WATCHDOG();
    }
    SPI0DAT = (addr | READ_BURST);
    SPI_WAIT();
    //SPI0DAT = 0;
    //SPI_WAIT();
    x = SPIGet();
    CC2500_NCS = 1;
   // SPI0CFG   = 0x70;       //CKPHA=1  CKPOL=1
    return x;
}// halSpiReadStatus



//-------------------------------------------------------------------------------------------------------
//  void halSpiReadBurstReg(BYTE addr, BYTE *buffer, BYTE count)
//
//  DESCRIPTION:
//      This function reads multiple CCxxx0 register, using SPI burst access.
//
//  ARGUMENTS:
//      BYTE addr
//          Address of the first CCxxx0 register to be accessed.
//      BYTE *buffer
//          Pointer to a byte array which stores the values read from a
//          corresponding range of CCxxx0 registers.
//      BYTE count
//          Number of bytes to be written to the subsequent CCxxx0 registers.
//-------------------------------------------------------------------------------------------------------
void halSpiReadBurstReg(BYTE addr, BYTE *buffer, BYTE count) {
    BYTE i;
  //  SPI0CFG   = 0x40;       //CKPHA=0  CKPOL=0
    CC2500_NCS = 0;
    while (CC2500_MISO)
    {
    	 ;//__RESET_WATCHDOG();
    }
    SPI0DAT = (addr | READ_BURST);
    SPI_WAIT();
    for (i = 0; i < count; i++) {
        //SPI0DAT = 0;
        //SPI_WAIT();
        buffer[i] = SPIGet();
    }
    CC2500_NCS = 1;
   // SPI0CFG   = 0x70;       //CKPHA=1  CKPOL=1
}// halSpiReadBurstReg

//-------------------------------------------------------------------------------------------------------
//  Bool halRfReceivePacket(BYTE *rxBuffer, UINT8 *length)
//
//  DESCRIPTION:
//      This function can be used to receive a packet of variable packet length (first byte in the packet
//      must be the length byte). The packet length should not exceed the RX FIFO size.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and
//      de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      Also, APPEND_STATUS in the PKTCTRL1 register must be enabled.
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.
//      After the GDO0 pin has been de-asserted, the RXBYTES register is read to make sure that there
//      are bytes in the FIFO. This is because the GDO signal will indicate sync received even if the
//      FIFO is flushed due to address filtering, CRC filtering, or packet length filtering.
//
//  ARGUMENTS:
//      BYTE *rxBuffer
//          Pointer to the buffer where the incoming data should be stored
//      UINT8 *length
//          Pointer to a variable containing the size of the buffer where the incoming data should be
//          stored. After this function returns, that variable holds the packet length.
//
//  RETURN VALUE:
//      Bool
//          TRUE:   CRC OK
//          FALSE:  CRC NOT OK
//-------------------------------------------------------------------------------------------------------
uchar halRfReceivePacket(uchar *rxBuffer, uchar *rssi) {
   uchar   packetLength,bufferlength;
    bufferlength = halSpiReadStatus(CCxxx0_RXBYTES);
   if (bufferlength& BYTES_IN_RXFIFO) {
   	  		packetLength = halSpiReadReg(CCxxx0_RXFIFO);
           if(packetLength>2&&packetLength<PHYDATALEN)
           {
            halSpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer,packetLength+2);
            // Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
				   	if(rxBuffer[packetLength+1]&CRC_OK)
				  	 {
				   			*rssi=rxBuffer[packetLength];
				   			halSpiStrobe(CCxxx0_SFRX);
					   		return (packetLength);
					  }
					}
	}
	halSpiStrobe(CCxxx0_SFRX);
	return FALSE;
}// halRfReceivePacketet
void CC2500_init()
{
    unsigned char * pbuffer;
    delayms(50);//power up
    POWER_UP_RESET_CCxxx0();
    halRfWriteRfSettings();//寫入配置寄存器
    halSpiWriteReg(CCxxx0_MCSM1,0x03);//發(fā)送完成轉接收
    pbuffer = (unsigned char *)paTable;
    halSpiWriteBurstReg(CCxxx0_PATABLE, pbuffer, sizeof(paTable));
   // if(halSpiReadStatus(0x30)==0x80)
   //  ; //       TEST_1=0;
}
/*
void CC2500_channel()
{
    halSpiStrobe(CCxxx0_SIDLE);
    halSpiWriteReg(CCxxx0_CHANNR,channel);
}*/