?? cstartup.lst
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1 # 1 "Compil/srcWinARM/Cstartup.S"
2 # 1 "<built-in>"
1 /*------------------------------------------------------------------------------
0
0
2 //*- ATMEL Microcontroller Software Support - ROUSSET -
3 //*------------------------------------------------------------------------------
4 //* The software is delivered "AS IS" without warranty or condition of any
5 //* kind, either express, implied or statutory. This includes without
6 //* limitation any warranty or condition with respect to merchantability or
7 //* fitness for any particular purpose, or against the infringements of
8 //* intellectual property rights of others.
9 //*-----------------------------------------------------------------------------
10 //*- File source : Cstartup.s
11 //*- Object : Generic CStartup for KEIL and GCC
12 //*- Compilation flag : None
13 //*-
14 //*- 1.0 18/Oct/04 JPP : Creation
15 //*- 1.1 21/Feb/05 JPP : Set Interrupt
16 //*- 1.1 01/Apr/05 JPP : save SPSR
17 //*
18 //*- WinARM/arm-elf-gcc-version by Martin Thomas - Modifications:
19 //* remapping-support, vector-location, stack-position and more...
20 //*-----------------------------------------------------------------------------*/
21
22 /*
23 20060902 (mth) : moved IRQ-Handler from section .vect* to
24 .init/.fastrun
25 */
26
27 /* check configuration-options and map to "assembler symbols": */
28
29 #ifdef ROM_RUN
30 .set RAM_MODE, 0
31 #ifdef VECTORS_IN_RAM
32 .set REMAP, 1
33 .set VECTREMAPPED, 1
34 #else
35 .set REMAP, 0
36 .set VECTREMAPPED, 0
37 #endif
38 #endif
39
40 #ifdef RAM_RUN
41 .set RAM_MODE, 1
42 .set REMAP, 1
43 .set VECTREMAPPED, 0
44 #endif
45
46
47 .if (RAM_MODE)
48 .print "RAM_MODE enabled"
49 .else
50 .print "ROM_MODE enabled"
51 .endif
52
53 .if (REMAP)
54 .print "remapping enabled"
55 .endif
56
57 .if (VECTREMAPPED)
58 .print "Vectors at start of RAM"
59 .else
60 .print "Vectors at start of Code"
61 .endif
62
63 .equ AIC_IVR, (256)
64 .equ AIC_FVR, (260)
65 .equ AIC_EOICR, (304)
66 .equ AT91C_BASE_AIC, (0xFFFFF000)
67
68 /*------------------------------------------------------------------------------
69 //*- Exception vectors
70 //*--------------------
71 //*- These vectors can be read at address 0 or at RAM address
72 //*- They ABSOLUTELY requires to be in relative addresssing mode in order to
73 //*- guarantee a valid jump. For the moment, all are just looping.
74 //*- If an exception occurs before remap, this would result in an infinite loop.
75 //*- To ensure if a exeption occurs before start application to infinite loop.
76 //*------------------------------------------------------------------------------*/
77
78 .if (VECTREMAPPED)
79 .print "Vectors in section .vectmapped -> .data"
80 .section .vectmapped, "ax"
81 .else
82 .print "Vectors in section .vectorg -> .text"
83 .section .vectorg, "ax"
84 .endif
85
86 0000 3CF09FE5 LDR PC,Reset_Addr /* 0x00 Reset handler */
87 0004 3CF09FE5 LDR PC,Undef_Addr /* 0x04 Undefined Instruction */
88 0008 3CF09FE5 LDR PC,SWI_Addr /* 0x08 Software Interrupt */
89 000c 3CF09FE5 LDR PC,PAbt_Addr /* 0x0C Prefetch Abort */
90 0010 3CF09FE5 LDR PC,DAbt_Addr /* 0x10 Data Abort */
91 0014 0000A0E1 NOP /* 0x14 reserved */
92 0018 38F09FE5 LDR PC,IRQ_Addr /* 0x18 IRQ */
93 fiqvec: /* 0x1c FIQ */
94 /*------------------------------------------------------------------------------
95 //*- Function : FIQ_Handler_Entry
96 //*- Treatments : FIQ Controller Interrupt Handler.
97 //*- Called Functions : AIC_FVR[interrupt]
98 //*------------------------------------------------------------------------------*/
99
100 FIQ_Handler_Entry:
101
102 /*- Switch in SVC/User Mode to allow User Stack access for C code */
103 /* because the FIQ is not yet acknowledged*/
104
105 /*- Save and r0 in FIQ_Register */
106 001c 0090A0E1 mov r9,r0
107 0020 040198E5 ldr r0 , [r8, #AIC_FVR]
108 0024 D3F021E3 msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
109
110 /*- Save scratch/used registers and LR in User Stack */
111 0028 0E502DE9 stmfd sp!, { r1-r3, r12, lr}
112
113 /*- Branch to the routine pointed by the AIC_FVR */
114 002c 0FE0A0E1 mov r14, pc
115 0030 10FF2FE1 bx r0
116
117 /*- Restore scratch/used registers and LR from User Stack */
118 0034 0E50BDE8 ldmia sp!, { r1-r3, r12, lr}
119
120 /*- Leave Interrupts disabled and switch back in FIQ mode */
121 0038 D1F021E3 msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
122
123 /*- Restore the R0 ARM_MODE_SVC register */
124 003c 0900A0E1 mov r0,r9
125
126 /*- Restore the Program Counter using the LR_fiq directly in the PC */
127 0040 04F05EE2 subs pc,lr,#4
128
129 /* end of fiqhandler */
130
131 0044 28000000 Reset_Addr: .word InitReset
132 0048 5C000000 Undef_Addr: .word Undef_Handler
133 /* SWI_Addr: .word SWI_Handler */
134 004c 00000000 SWI_Addr: .word SoftwareInterruptASM /* in swi_handler.S */
135 0050 60000000 PAbt_Addr: .word PAbt_Handler
136 0054 64000000 DAbt_Addr: .word DAbt_Handler
137 0058 00000000 IRQ_Addr: .word IRQ_Handler_Entry
138
139 005c FEFFFFEA Undef_Handler: B Undef_Handler
140 /* SWI_Handler: B SWI_Handler */
141 0060 FEFFFFEA PAbt_Handler: B PAbt_Handler
142 0064 FEFFFFEA DAbt_Handler: B DAbt_Handler
143
144
145 .arm
146 .section .init, "ax"
147 .global _startup
148 .func _startup
149 _startup:
150 reset:
151
152 .if (VECTREMAPPED)
153 /* mthomas: Dummy used during startup */
154 0000 F4F09FE5 LDR PC,=Reset_Addr_F
155 0004 0000A0E1 NOP
156 0008 0000A0E1 NOP
157 000c 0000A0E1 NOP
158 0010 0000A0E1 NOP
159 0014 0000A0E1 NOP /*.word 0xdeadbeef*/ /* NOP */ /* Reserved Address */
160 0018 0000A0E1 NOP
161 001c 0000A0E1 NOP
162 0020 28000000 Reset_Addr_F: .word InitReset
163 .endif
164
165 .RAM_TOP:
166 0024 00000000 .word __TOP_STACK
167
168 InitReset:
169
170 /*------------------------------------------------------------------------------
171 /*- Remapping
172 /*------------------------------------------------------------------------------*/
173 .if (VECTREMAPPED)
174 .print "RCR setting for remapping enabled"
175 .equ MC_BASE,0xFFFFFF00 /* MC Base Address */
176 .equ MC_RCR, 0x00 /* MC_RCR Offset */
177
178
179 /* store first word in RAM into r4 */
180 0028 D0009FE5 ldr r0,=__FIRST_IN_RAM
181 002c 004090E5 ldr r4,[r0]
182 /* load value at address 0 into R2 */
183 0030 0010A0E3 ldr r1,=0x00000000
184 0034 002091E5 ldr r2,[r1]
185 /* xor value from address 0 (flip all bits), store in R3 */
186 0038 0030E0E3 ldr r3,=0xffffffff
187 003c 033022E0 eor r3, r2, r3
188 /* write xored value to first word in RAM
189 if already remapped this will also change
190 the value at 0 */
191 0040 003080E5 str r3,[r0]
192 /* load from address 0 again into R3 */
193 0044 003091E5 ldr r3,[r1]
194 /* restore first value in RAM */
195 0048 004080E5 str r4,[r0]
196
197 /* compare */
198 004c 020053E1 cmp r3, r2
199 0050 0200001A bne already_remapped
200
201 /* if both values have been equal the change of the
202 RAM-value had no effect on the value at 0x00000000
203 so we are not remapping yet -> remap now: */
204 0054 FF00E0E3 LDR R0, =MC_BASE
205 0058 0110A0E3 MOV R1, #1
206 005c 001080E5 STR R1, [R0, #MC_RCR]
207
208 already_remapped:
209 .endif
210
211
212 /*------------------------------------------------------------------------------
213 /*- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit
214 /*------------------------------------------------------------------------------*/
215 .extern AT91F_LowLevelInit
216 /*- minumum C initialization */
217 /*- call AT91F_LowLevelInit( void) */
218
219 0060 44D01FE5 ldr r13,.RAM_TOP /* temporary stack in internal RAM (**) */
220 /*--Call Low level init function in ABSOLUTE through the Interworking */
221 0064 98009FE5 ldr r0,=AT91F_LowLevelInit
222 0068 0FE0A0E1 mov lr, pc
223 006c 10FF2FE1 bx r0
224 /*------------------------------------------------------------------------------
225 //*- Stack Sizes Definition
226 //*------------------------
227 //*- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
228 //*- the vectoring. This assume that the IRQ management.
229 //*- The Interrupt Stack must be adjusted depending on the interrupt handlers.
230 //*- Fast Interrupt not requires stack If in your application it required you must
231 //*- be definehere.
232 //*- The System stack size is not defined and is limited by the free internal
233 //*- SRAM.
234 //*------------------------------------------------------------------------------*/
235
236 /*------------------------------------------------------------------------------
237 //*- Top of Stack Definition
238 //*-------------------------
239 //*- Interrupt and Supervisor Stack are located at the top of internal memory in
240 //*- order to speed the exception handling context saving and restoring.
241 //*- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
242 //*------------------------------------------------------------------------------*/
243
244 .EQU IRQ_STACK_SIZE, (3*8*4)
245 .EQU ARM_MODE_FIQ, 0x11
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