module LCD
(
	CLOCK_50,
	SW,
	LEDR,
	
	LCD_ON, LCD_BLON, LCD_EN,
	LCD_RS, LCD_RW,
	LCD_DATA
);

input CLOCK_50;
input [17:0] SW;
output reg [17:0] LEDR;

output LCD_ON, LCD_BLON, LCD_EN;
output LCD_RS, LCD_RW;
inout [7:0] LCD_DATA;

reg [26:0] count;
reg [7:0] data;
reg on,blon,en,rs,rw;
reg [3:0] state;
reg FlagBusy;

assign LCD_ON = on;
assign LCD_BLON = blon;
assign LCD_EN = en;
assign LCD_RS = rs;
assign LCD_RW = rw;
assign LCD_DATA = (!rw)? data : 8'hzz;

initial
begin
	on <= 1'b1;
	blon <= 1'b0;
	en <= 1'b1;
	rs <= 1'b0;
	rw <= 1'b0;
	data <= 8'b0;
	state <= 4'b0;
	LEDR[15:0] <= 16'h0000;
end


always @ (posedge CLOCK_50)
begin
	count <= count + 1'b1;
end

always @ (posedge count[24])
begin
	case (state)
	4'h0: // start
	begin
		en <= 1'b1;
		LEDR[state] <= 1'b1;
		state <= state + 4'h1;
	end
	4'h1: // 03
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h30; 
		state <= state + 4'h1;
	end
	4'h2: // 03
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h30; 
		state <= state + 4'h1;
	end
	4'h3: // 03
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h30; 
		state <= state + 4'h1;
	end
	4'h4: // 001D NFXX
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h38; 
		state <= state + 4'h1;
	end
	4'h5: // 0e
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h0e; 
		state <= state + 4'h1;
	end
	4'h6: // 01
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h01; 
		state <= state + 4'h1;
	end
	4'h7: // 00000 001-
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h03; 
		state <= state + 4'h1;
	end
	4'h8: // SHOW
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h0c; 
		state <= state + 4'h1;
	end
	4'h9: // 0 1 ID SH
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h06; 
		state <= state + 4'h1;
	end
	4'ha:
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b1;
		en <= 1'b0;
		FlagBusy <= LCD_DATA[6]; 
		state <= state + 4'h1;
	end
	4'hb: 
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		if (FlagBusy == 1'b0)
		begin
			en <= 1'b1;
			state <= state + 4'h1;
		end
		else
		begin
			rs <= 1'b0;
			rw <= 1'b1;
			FlagBusy <= LCD_DATA[7];
		end
	end
	4'hc: // DDRAM address
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b0;
		rw <= 1'b0;
		data <= 8'h00; 
		state <= state + 4'h1;
	end
	4'hd: // data
	begin
		LEDR[state-4'h1] <= 1'b0;
		LEDR[state] <= 1'b1;
		rs <= 1'b1;
		rw <= 1'b0;
		data <= 8'h30;
		state <= state + 4'h1;
	end
	4'he: 
	begin
		en <= 1'b0; 
	end
	default: 
	begin
		state <= 4'h0;
		LEDR[15:0] <= 16'h0000;
	end 
	endcase
end

endmodule