module LCD
(
	CLOCK_50,
	SW,
	LEDR,
	
	LCD_ON, LCD_BLON, LCD_EN,
	LCD_RS, LCD_RW,
	LCD_DATA
);

input CLOCK_50;
input [17:0] SW;
output reg [17:0] LEDR;

output LCD_ON, LCD_BLON, LCD_EN;
output LCD_RS, LCD_RW;
inout [7:0] LCD_DATA;

reg [8:0] data;
reg on,blon,en,rw;

reg [5:0] State;
reg [2:0] Index;

reg Flag;
reg [19:0] Count;
reg [19:0] CountEnd;

assign LCD_ON = on;
assign LCD_BLON = blon;
assign LCD_EN = en;
assign LCD_RS = data[8];
assign LCD_RW = rw;
assign LCD_DATA = (!rw)? data[7:0] : 8'hzz;

initial
begin
	on <= 1'b1;
	blon <= 1'b0;
	en <= 1'b0;
	rw <= 1'b0;
	data <= 9'b0;
	State <= 6'b0;
	Flag <= 1;
	Index <= 0;
	CountEnd <= 20'hFFFFF;
end

always @ (posedge CLOCK_50)
begin
	if (Flag == 1)
	begin
		if (Count < CountEnd)
			Count <= Count + 20'b1;
		else
		begin
			Count <= 20'b0;
		end
	end
end

always @ (posedge CLOCK_50 & State < 6'h29)
begin
	case (Index)
		3'h0: 
		begin
			//LEDR[Index] <= 1;
			if(Count == CountEnd)
			begin
				Flag <= 0;
				if (State < 6'h29)
					State <= State + 1;
				Index <= Index + 1;
			end
		end
		3'h1: Index <= Index + 1;
		3'h2:
		begin
			//LEDR[Index] <= 1;
			//LEDR[Index-1] <= 0;
			en <= 1;
			Flag <= 1;
			CountEnd <= 8'h10;
			Index <= Index + 1;
		end
		3'h3:
		begin
			//LEDR[Index] <= 1;
			//LEDR[Index-1] <= 0;
			if(Count == CountEnd)
			begin
				en <= 0;
				Flag <= 1;
				CountEnd <= 20'h40000;
				Index <= 0;
			end
		end
		default: Index <= 0;
	endcase
end
	
//always @ (State)
always @ (posedge CLOCK_50)
begin
	case (State)
		////	initial	////
		6'h00: data <= 9'h030;
		6'h01: data <= 9'h030;	
		6'h02: data <= 9'h030;
		6'h03: data <= 9'h038;
		6'h04: data <= 9'h00c;
		6'h05: data <= 9'h001;		6'h06: data <= 9'h006;
		////	address	////		6'h07: data <= 9'h080;
		////	data	////
		6'h08: data <= 9'h1f7;
		6'h09: data <= 9'h120;
		6'h0a: data <= 9'h13d;
		6'h0b: data <= 9'h120;
				6'h0c: data <= 9'h133;
		6'h0d: data <= 9'h12E;
		6'h0e: data <= 9'h131;
		6'h0f: data <= 9'h134;
		
		6'h10: data <= 9'h131;
		6'h11: data <= 9'h135;
		6'h12: data <= 9'h139;
		6'h13: data <= 9'h132;
		
		6'h14: data <= 9'h136;
		6'h15: data <= 9'h135;
		6'h16: data <= 9'h133;
		6'h17: data <= 9'h135;
		
		////	address	////
		6'h18: data <= 9'h0C0;
		////	data	////
		6'h19: data <= 9'h138;		6'h1a: data <= 9'h139;		6'h1b: data <= 9'h137;
		6'h1c: data <= 9'h139;
		
		6'h1d: data <= 9'h133;
		6'h1e: data <= 9'h132;		6'h1f: data <= 9'h133;
		6'h20: data <= 9'h138;
		
		6'h21: data <= 9'h134;
		6'h22: data <= 9'h136;
		6'h23: data <= 9'h132;
		6'h24: data <= 9'h136;
		
		6'h25: data <= 9'h134;
		6'h26: data <= 9'h133;		6'h27: data <= 9'h133;		6'h28: data <= 9'h138;

		default: data <= 9'h000;
	endcase
end




endmodule