+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2C35F672C6                   ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------------+---------+------------------+---------------------+-----------+----------------+------------------+------------------+-----------------------+
; Node                                                                                                                                     ; Action  ; Operation        ; Reason              ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
+------------------------------------------------------------------------------------------------------------------------------------------+---------+------------------+---------------------+-----------+----------------+------------------+------------------+-----------------------+
; BinToDec:BTD1|lpm_divide:Mod1|lpm_divide_35m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_mve:divider|add_sub_6_result_int[0]~12 ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                ;                  ;                  ;                       ;
; BinToDec:BTD2|lpm_divide:Mod1|lpm_divide_35m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_mve:divider|add_sub_6_result_int[0]~12 ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                ;                  ;                  ;                       ;
+------------------------------------------------------------------------------------------------------------------------------------------+---------+------------------+---------------------+-----------+----------------+------------------+------------------+-----------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.pin.


+--------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                ;
+---------------------------------------------+----------------------------------------------------------------+
; Resource                                    ; Usage                                                          ;
+---------------------------------------------+----------------------------------------------------------------+
; Total logic elements                        ; 235 / 33,216 ( < 1 % )                                         ;
;     -- Combinational with no register       ; 183                                                            ;
;     -- Register only                        ; 16                                                             ;
;     -- Combinational with a register        ; 36                                                             ;
;                                             ;                                                                ;
; Logic element usage by number of LUT inputs ;                                                                ;
;     -- 4 input functions                    ; 60                                                             ;
;     -- 3 input functions                    ; 52                                                             ;
;     -- <=2 input functions                  ; 107                                                            ;
;     -- Register only                        ; 16                                                             ;
;                                             ;                                                                ;
; Logic elements by mode                      ;                                                                ;
;     -- normal mode                          ; 151                                                            ;
;     -- arithmetic mode                      ; 68                                                             ;
;                                             ;                                                                ;
; Total registers*                            ; 52 / 34,593 ( < 1 % )                                          ;