?? unsignmulti.map.rpt
字號:
Analysis & Synthesis report for UnsignMulti
Sun Jul 13 17:08:01 2008
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis DSP Block Usage Summary
8. Registers Removed During Synthesis
9. General Register Statistics
10. Inverted Register Statistics
11. Parameter Settings for User Entity Instance: BinDis:BD1
12. Parameter Settings for User Entity Instance: BinDis:BD2
13. Parameter Settings for User Entity Instance: BinDis:BD3
14. Parameter Settings for Inferred Entity Instance: BinMulti:BM1|lpm_mult:Mult0
15. Parameter Settings for Inferred Entity Instance: BinToDec:BTD0|lpm_divide:Mod0
16. Parameter Settings for Inferred Entity Instance: BinToDec:BTD0|lpm_divide:Mod1
17. Parameter Settings for Inferred Entity Instance: BinToDec:BTD0|lpm_divide:Div1
18. Parameter Settings for Inferred Entity Instance: BinToDec:BTD0|lpm_divide:Div0
19. Parameter Settings for Inferred Entity Instance: BinToDec:BTD1|lpm_divide:Mod0
20. Parameter Settings for Inferred Entity Instance: BinToDec:BTD1|lpm_divide:Mod1
21. Parameter Settings for Inferred Entity Instance: BinToDec:BTD1|lpm_divide:Div1
22. Parameter Settings for Inferred Entity Instance: BinToDec:BTD2|lpm_divide:Mod0
23. Parameter Settings for Inferred Entity Instance: BinToDec:BTD2|lpm_divide:Mod1
24. Parameter Settings for Inferred Entity Instance: BinToDec:BTD2|lpm_divide:Div1
25. lpm_mult Parameter Settings by Entity Instance
26. Analysis & Synthesis Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Jul 13 17:08:01 2008 ;
; Quartus II Version ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name ; UnsignMulti ;
; Top-level Entity Name ; UnsignMulti ;
; Family ; Cyclone II ;
; Total logic elements ; 218 ;
; Total combinational functions ; 218 ;
; Dedicated logic registers ; 52 ;
; Total registers ; 52 ;
; Total pins ; 105 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 1 ;
; Total PLLs ; 0 ;
+------------------------------------+-----------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; UnsignMulti ; UnsignMulti ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone II/Cyclone III ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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