{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 UnsignMulti.v(77) " "Warning (10230): Verilog HDL assignment warning at UnsignMulti.v(77): truncated value with size 8 to match size of target (4)" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BinDis BinDis:BD1 " "Info: Elaborating entity \"BinDis\" for hierarchy \"BinDis:BD1\"" {  } { { "UnsignMulti.v" "BD1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 23 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BinDis BinDis:BD3 " "Info: Elaborating entity \"BinDis\" for hierarchy \"BinDis:BD3\"" {  } { { "UnsignMulti.v" "BD3" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 25 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DecDis DecDis:DD2 " "Info: Elaborating entity \"DecDis\" for hierarchy \"DecDis:DD2\"" {  } { { "UnsignMulti.v" "DD2" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 27 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ordered port 0 BTD2 4 8 " "Warning (12010): Port \"ordered port 0\" on the entity instantiation of \"BTD2\" is connected to a signal of width 4. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "UnsignMulti.v" "BTD2" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 21 0 0 } }  } 0 12010 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ordered port 0 BTD1 4 8 " "Warning (12010): Port \"ordered port 0\" on the entity instantiation of \"BTD1\" is connected to a signal of width 4. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "UnsignMulti.v" "BTD1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 20 0 0 } }  } 0 12010 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "11 " "Info: Inferred 11 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "BinMulti:BM1\|Mult0 lpm_mult " "Info: Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"BinMulti:BM1\|Mult0\"" {  } { { "UnsignMulti.v" "Mult0" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 49 -1 0 } }  } 0 0 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD0\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD0\|Mod0\"" {  } { { "UnsignMulti.v" "Mod0" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD0\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD0\|Mod1\"" {  } { { "UnsignMulti.v" "Mod1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 77 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD0\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD0\|Div1\"" {  } { { "UnsignMulti.v" "Div1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD0\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD0\|Div0\"" {  } { { "UnsignMulti.v" "Div0" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 75 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD1\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD1\|Mod0\"" {  } { { "UnsignMulti.v" "Mod0" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD1\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD1\|Mod1\"" {  } { { "UnsignMulti.v" "Mod1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 77 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD1\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD1\|Div1\"" {  } { { "UnsignMulti.v" "Div1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD2\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD2\|Mod0\"" {  } { { "UnsignMulti.v" "Mod0" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD2\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD2\|Mod1\"" {  } { { "UnsignMulti.v" "Mod1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 77 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "BinToDec:BTD2\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"BinToDec:BTD2\|Div1\"" {  } { { "UnsignMulti.v" "Div1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" 284 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "BinMulti:BM1\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"BinMulti:BM1\|lpm_mult:Mult0\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 49 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_lq01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_lq01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_lq01 " "Info: Found entity 1: mult_lq01" {  } { { "db/mult_lq01.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/mult_lq01.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "BinToDec:BTD0\|lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"BinToDec:BTD0\|lpm_divide:Mod0\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_75m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_75m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_75m " "Info: Found entity 1: lpm_divide_75m" {  } { { "db/lpm_divide_75m.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/lpm_divide_75m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_ekh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_ekh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_ekh " "Info: Found entity 1: sign_div_unsign_ekh" {  } { { "db/sign_div_unsign_ekh.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/sign_div_unsign_ekh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_uve.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_uve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_uve " "Info: Found entity 1: alt_u_div_uve" {  } { { "db/alt_u_div_uve.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/alt_u_div_uve.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "BinToDec:BTD0\|lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"BinToDec:BTD0\|lpm_divide:Mod1\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 77 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_35m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_35m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_35m " "Info: Found entity 1: lpm_divide_35m" {  } { { "db/lpm_divide_35m.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/lpm_divide_35m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Info: Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/sign_div_unsign_akh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}