--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=4 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=4 SKIP_BITS=0 denominator numerator quotient remainder
--VERSION_BEGIN 7.2SP3 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION alt_u_div_gve (denominator[3..0], numerator[3..0])
RETURNS ( den_out[3..0], quotient[3..0], remainder[3..0]);

--synthesis_resources = lut 14 
SUBDESIGN sign_div_unsign_7kh
( 
	denominator[3..0]	:	input;
	numerator[3..0]	:	input;
	quotient[3..0]	:	output;
	remainder[3..0]	:	output;
) 
VARIABLE 
	divider : alt_u_div_gve;
	adder_result_int[4..0]	:	WIRE;
	adder_cin	:	WIRE;
	adder_dataa[3..0]	:	WIRE;
	adder_datab[3..0]	:	WIRE;
	adder_result[3..0]	:	WIRE;
	gnd_wire	: WIRE;
	norm_num[3..0]	: WIRE;
	protect_quotient[3..0]	: WIRE;
	protect_remainder[3..0]	: WIRE;

BEGIN 
	divider.denominator[] = denominator[];
	divider.numerator[] = norm_num[];
	adder_result_int[] = (adder_dataa[], 0) - (adder_datab[], !adder_cin);
	adder_result[] = adder_result_int[4..1];
	adder_cin = gnd_wire;
	adder_dataa[] = denominator[];
	adder_datab[] = protect_remainder[];
	gnd_wire = B"0";
	norm_num[] = numerator[];
	protect_quotient[] = divider.quotient[];
	protect_remainder[] = divider.remainder[];
	quotient[] = protect_quotient[];
	remainder[] = protect_remainder[];
END;
--VALID FILE