--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=1 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 7.2SP3 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION sign_div_unsign_7kh (denominator[3..0], numerator[3..0])
RETURNS ( quotient[3..0], remainder[3..0]);

--synthesis_resources = lut 14 
SUBDESIGN lpm_divide_t4m
( 
	denom[3..0]	:	input;
	numer[0..0]	:	input;
	quotient[0..0]	:	output;
	remain[3..0]	:	output;
) 
VARIABLE 
	divider : sign_div_unsign_7kh;
	gnd_wire	: WIRE;
	num_padder[2..0]	: WIRE;
	numer_tmp[3..0]	: WIRE;

BEGIN 
	divider.denominator[] = denom[];
	divider.numerator[] = numer_tmp[];
	gnd_wire = B"0";
	num_padder[] = ( gnd_wire, gnd_wire, gnd_wire);
	numer_tmp[] = ( num_padder[], numer[]);
	quotient[0..0] = divider.quotient[0..0];
	remain[] = divider.remainder[];
END;
--VALID FILE