source "core_files.tcl"add_file -constraint "core.sdc"impl -add synset_option -technology VIRTEX-Eset_option -part XCV1000Eset_option -package FG1156set_option -speed_grade -6set_option -default_enum_encoding onehotset_option -symbolic_fsm_compiler 0set_option -resource_sharing 0set_option -use_fsm_explorer 0set_option -top_module "core"set_option -frequency 45.000set_option -fanout_limit 100set_option -disable_io_insertion 0set_option -pipe 1set_option -modular 0set_option -retiming 1set_option -write_verilog 0set_option -write_vhdl 0set_option -write_apr_constraint 0project -result_file "./core.edf"set_option -compiler_compatible 0impl -active "syn"