/******************************************************************************/
/*  EDMA.H - TMS320C64 Peripheral Support Library SPORTS Support             */
/******************************************************************************/
#ifndef _EDMA_H_
#define _EDMA_H_

#define EDMA_CHANNEL_NUM     32

/* Define EDMA Registers */
#define PQSR		0x01A0FFE0	/* Address of priority queue status     */
#define CIPRL		0x01A0FFE4	/* Address of channel interrupt pending */
#define CIERL		0x01A0FFE8	/* Address of channel interrupt enable  */
#define CCERL		0x01A0FFEC	/* Address of channel chain enable      */

#define CIPRH		0x01A0FFA4	/* Address of channel interrupt pending */
#define CIERH		0x01A0FFA8	/* Address of channel interrupt enable  */
#define CCERH		0x01A0FFAC	/* Address of channel chain enable      */

#define ERL			0x01A0FFF0	/* Address of event register            */
#define EERL		0x01A0FFF4	/* Address of event enable register     */
#define ECRL		0x01A0FFF8	/* Address of event clear register      */
#define ESRL		0x01A0FFFC	/* Address of event set register        */

#define ERH	    	0x01A0FFB0	/* Address of event register            */
#define EERH		0x01A0FFB4	/* Address of event enable register     */
#define ECRH		0x01A0FFB8	/* Address of event clear register      */
#define ESRH		0x01A0FFBC	/* Address of event set register        */

/* Define EDMA Transfer Parameter Entry Fields */
#define OPT			0*4			/* Options Parameter                    */
#define SRC			1*4			/* SRC Address Parameter                */
#define CNT			2*4			/* Count Parameter                      */
#define DST			3*4			/* DST Address Parameter                */
#define IDX			4*4			/* IDX Parameter                        */
#define LNK			5*4			/* LNK Parameter                        */

   					
/* Define EDMA Parameter RAM Addresses */ 
#define EVENT0_PARAMS           0x01A00000
#define EVENT_PARAMS_ADDR(chan) \
        (EVENT0_PARAMS + ((chan) * 0x18))
        
#define NULL_PARAMS_ADDR        0x01A007E0

/* Define QDMA Memory Mapped Registers */
#define QDMA_OPT		0x02000000	/* Address of QDMA options register     */
#define QDMA_SRC		0x02000004	/* Address of QDMA SRC address register */
#define QDMA_CNT		0x02000008	/* Address of QDMA counts register      */
#define QDMA_DST		0x0200000C	/* Address of QDMA DST address register */
#define QDMA_IDX		0x02000010	/* Address of QDMA index register       */

/* Define QDMA Pseudo Registers */
#define QDMA_S_OPT		0x02000020	/* Address of QDMA options register     */
#define QDMA_S_SRC		0x02000024	/* Address of QDMA SRC address register */
#define QDMA_S_CNT		0x02000028	/* Address of QDMA counts register      */
#define QDMA_S_DST		0x0200002C	/* Address of QDMA DST address register */
#define QDMA_S_IDX		0x02000030	/* Address of QDMA index register       */

/* The options parameter (OPT) in the EDMA/QDMA channel entry */
#define FS               0          /* Frame synchronization   */          
#define LINK             1          /* Link (not in QDMA)      */
#define TCC             16          /* Transfer complete code  */
#define TCINT           20          /* TCINT                   */
#define DUM             21          /* Destination address update mode */
#define DD              23          /* Destination dimension   */
#define SUM             24          /* Source address update mode      */
#define DS              26          /* Source dimension        */ 
#define ESIZE           27          /* Element size            */
#define PRI             29          /* Priority levels for EDMA events */
/* C64xonly(OPT) */
#define PDTD             2          /* Peripheral device transfer (PDT) mode for destination */
#define PDTS             3          /* Peripheral device transfer (PDT) mode for source      */
#define ATCC             5          /* Alternate transfer complete code                      */
#define ATCINT          12          /* Alternate transfer complete interrupt                 */
#define TCCM            13          /* Most significant bits of transfer complete code       */

/* Define EDMA Parameter RAM Addresses */ 
//#define EVENT0_PARAMS 0x01A00000
#define EVENT1_PARAMS EVENT0_PARAMS + 0x18
#define EVENT2_PARAMS EVENT1_PARAMS + 0x18
#define EVENT3_PARAMS EVENT2_PARAMS + 0x18
#define EVENT4_PARAMS EVENT3_PARAMS + 0x18
#define EVENT5_PARAMS EVENT4_PARAMS + 0x18
#define EVENT6_PARAMS EVENT5_PARAMS + 0x18
#define EVENT7_PARAMS EVENT6_PARAMS + 0x18
#define EVENT8_PARAMS EVENT7_PARAMS + 0x18
#define EVENT9_PARAMS EVENT8_PARAMS + 0x18
#define EVENTA_PARAMS EVENT9_PARAMS + 0x18
#define EVENTB_PARAMS EVENTA_PARAMS + 0x18
#define EVENTC_PARAMS EVENTB_PARAMS + 0x18
#define EVENTD_PARAMS EVENTC_PARAMS + 0x18
#define EVENTE_PARAMS EVENTD_PARAMS + 0x18
#define EVENTF_PARAMS EVENTE_PARAMS + 0x18
#define EVENTN_PARAMS EVENTF_PARAMS + 0x18
#define EVENTO_PARAMS EVENTN_PARAMS + 0x18

#define ADDRESS_FIX_MODE	0
#define ADDRESS_INC_MODE	1

#define EDMA_NOTLINK_MODE   0
#define EDMA_AUTOLINK_MODE  1

#define QDMA_TCC        8
#define QDMA_PRI	2	//DSP內(nèi)部DMA
#define EDMA_PRI	1	//DSP間數(shù)據(jù)通信



typedef   struct
{
  unsigned int	
  				opt,
  				src,
   				cnt,
  				dst,
  				idx,
  				lnk;
}
EDMA_REG ;



void qdma_start(int src, int dst, int sum, int dum, int size);
int  qdma_2Dto1D_start(int src, int dst, int image_size_x, int image_size_y,
						int LU_x, int LU_y, int RD_x, int RD_y,
						unsigned char nbytePerPixel);
int  edma_1Dto2D_start(int src, int dst, unsigned int  ch, int image_size_x, int image_size_y,
						int LU_x, int LU_y, int RD_x, int RD_y,
						unsigned char nbytePerPixel);
int  edma_2Dto1D_start(int src, int dst, unsigned int  ch, int image_size_x, int image_size_y,
						int LU_x, int LU_y, int RD_x, int RD_y,
						unsigned char nbytePerPixel);
int edma_start(int src, int dst, unsigned int ch, int sum, int dum, int islink, int size);
void edma_null_init();
#endif /* ifndef _EDMA_H_ */