Protel Design System Design Rule Check
PCB File : \Documents and Settings\taoyong\桌面\點(diǎn)陣\protel電路圖\PCB1.PcbDoc
Date     : 2008-8-2
Time     : 21:14:08

WARNING: Zero hole size multi-layer pad(s) detected
   Pad J2-1(4480mil,9919.37mil)  Multi-Layer on Net NetJ2_1
   Pad J2-2(4480mil,9675.276mil)  Multi-Layer on Net GND
   Pad J2-3(4676.85mil,9793.386mil)  Multi-Layer on Net GND
Total: 3

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
   Violation         Pad J2-1(4480mil,9919.37mil)  Multi-Layer  Actual Hole Size = 0mil
   Violation         Pad J2-2(4480mil,9675.276mil)  Multi-Layer  Actual Hole Size = 0mil
   Violation         Pad J2-3(4676.85mil,9793.386mil)  Multi-Layer  Actual Hole Size = 0mil
Rule Violations :3

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=60mil) (Preferred=10mil) (InNet('GND'))
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=8mil) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0


Violations Detected : 3
Time Elapsed        : 00:00:01