library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qiangdaqi is 
    port(clk : in std_logic;
         clk2: in std_logic;
         sel : in std_logic;
         clr : in std_logic;
         star: in std_logic; 
         din : in std_logic;
         data: in std_logic_vector(7 downto 0);
         ring: out std_logic;
         t3  : buffer std_logic;
         t4  : out std_logic;
         qh  : buffer std_logic_vector(1 downto 0);
         q1,q2,q3:buffer std_logic_vector(3 downto 0));
end;
architecture one of qiangdaqi is  
signal cout1: std_logic; 
  component qiangda 
       port(data : in std_logic_vector(7 downto 0);
            q:     buffer std_logic_vector(3 downto 0);
            cout:  buffer std_logic;
            t3  :  in std_logic;
            clr:   in std_logic);
       end component;
 component cnt10
      port(sel   :in std_logic_vector(1 downto 0);
           q1,q2 : buffer std_logic_vector(3 downto 0);
           clr   : in  std_logic;
           star  : in  std_logic;
           clk   : in  std_logic;
           in0   : in  std_logic;
           clk3  : in  std_logic;
           din   : in  std_logic;
           t3    : buffer std_logic;
           t4    : buffer std_logic;
           ring  : out std_logic);
        end component;
component  sel0 
       port(sel : in std_logic;
            clk2 :in std_logic;
            q   :out std_logic_vector(1 downto 0));
        end component;
   begin
      u1:    sel0  port map(sel=>sel,q=>qh,clk2=>clk2 );
      u2: qiangda  port map(data=>data,t3=>t3,clr=>clr,cout=>cout1,q=>q3);
      u3:   cnt10  port map(sel=>qh,clr=>clr,star=>star,clk=>clk,in0=>cout1,q1=>q1,q2=>q2,clk3=>clk2,ring=>ring,din=>din,t3=>t3,t4=>t4);
end one;