library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qiangda is
  port(data : in std_logic_vector(7 downto 0);
       q:     buffer std_logic_vector(3 downto 0);
       cout:  buffer std_logic;
       t3  :  in std_logic;
       clr:   in std_logic); 
end ;
architecture one of qiangda is
    begin 
  process(data,clr,t3)
    begin 
      if clr='0' then cout<='0';q<="0000";
      elsif t3 = '1' then 
        if cout='0' then  
         case data is
            when "00000000" => q<="0000";
            when "00000001" => q<="0001"; cout<='1';
            when "00000010" => q<="0010"; cout<='1';
            when "00000100" => q<="0011"; cout<='1';
            when "00001000" => q<="0100"; cout<='1';
            when "00010000" => q<="0101"; cout<='1';
            when "00100000" => q<="0110"; cout<='1';
            when "01000000" => q<="0111"; cout<='1';
            when "10000000" => q<="1000"; cout<='1';
            when others =>null;
            end case;
        else  q<=q; cout<=cout;
     end if;
  end if;
end process;
end;