{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 10 00:48:05 2008 " "Info: Processing started: Thu Jul 10 00:48:05 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt10-one " "Info: Found design unit 1: cnt10-one" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt10 " "Info: Found entity 1: cnt10" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qiangda.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file qiangda.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 qiangda-one " "Info: Found design unit 1: qiangda-one" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 qiangda " "Info: Found entity 1: qiangda" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qiangdaqi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file qiangdaqi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 qiangdaqi-one " "Info: Found design unit 1: qiangdaqi-one" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 qiangdaqi " "Info: Found entity 1: qiangdaqi" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sel0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sel0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sel0-one " "Info: Found design unit 1: sel0-one" {  } { { "sel0.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/sel0.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sel0 " "Info: Found entity 1: sel0" {  } { { "sel0.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/sel0.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "qiangdaqi " "Info: Elaborating entity \"qiangdaqi\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sel0 sel0:u1 " "Info: Elaborating entity \"sel0\" for hierarchy \"sel0:u1\"" {  } { { "qiangdaqi.vhd" "u1" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 41 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "t1 sel0.vhd(19) " "Warning (10492): VHDL Process Statement warning at sel0.vhd(19): signal \"t1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "sel0.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/sel0.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "t2 sel0.vhd(20) " "Warning (10492): VHDL Process Statement warning at sel0.vhd(20): signal \"t2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "sel0.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/sel0.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "qiangda qiangda:u2 " "Info: Elaborating entity \"qiangda\" for hierarchy \"qiangda:u2\"" {  } { { "qiangdaqi.vhd" "u2" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cout qiangda.vhd(15) " "Warning (10492): VHDL Process Statement warning at qiangda.vhd(15): signal \"cout\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 15 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q qiangda.vhd(28) " "Warning (10492): VHDL Process Statement warning at qiangda.vhd(28): signal \"q\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cout qiangda.vhd(28) " "Warning (10492): VHDL Process Statement warning at qiangda.vhd(28): signal \"cout\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "cout qiangda.vhd(12) " "Warning (10631): VHDL Process Statement warning at qiangda.vhd(12): inferring latch(es) for signal or variable \"cout\", which holds its previous value in one or more paths through the process" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "q qiangda.vhd(12) " "Warning (10631): VHDL Process Statement warning at qiangda.vhd(12): inferring latch(es) for signal or variable \"q\", which holds its previous value in one or more paths through the process" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[0\] qiangda.vhd(12) " "Info (10041): Inferred latch for \"q\[0\]\" at qiangda.vhd(12)" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[1\] qiangda.vhd(12) " "Info (10041): Inferred latch for \"q\[1\]\" at qiangda.vhd(12)" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}