{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[2\] qiangda.vhd(12) " "Info (10041): Inferred latch for \"q\[2\]\" at qiangda.vhd(12)" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "q\[3\] qiangda.vhd(12) " "Info (10041): Inferred latch for \"q\[3\]\" at qiangda.vhd(12)" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "cout qiangda.vhd(12) " "Info (10041): Inferred latch for \"cout\" at qiangda.vhd(12)" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt10 cnt10:u3 " "Info: Elaborating entity \"cnt10\" for hierarchy \"cnt10:u3\"" {  } { { "qiangdaqi.vhd" "u3" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 43 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sel cnt10.vhd(28) " "Warning (10492): VHDL Process Statement warning at cnt10.vhd(28): signal \"sel\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk3 cnt10.vhd(63) " "Warning (10492): VHDL Process Statement warning at cnt10.vhd(63): signal \"clk3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 63 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt10:u3\|q2\[0\]~16 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt10:u3\|q2\[0\]~16\"" {  } { { "cnt10.vhd" "q2\[0\]~16" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 27 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "cnt10:u3\|lpm_counter:q2_rtl_0 " "Info: Elaborated megafunction instantiation \"cnt10:u3\|lpm_counter:q2_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "cnt10:u3\|lpm_counter:q2_rtl_0 " "Info: Instantiated megafunction \"cnt10:u3\|lpm_counter:q2_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION DOWN " "Info: Parameter \"LPM_DIRECTION\" = \"DOWN\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter cnt10:u3\|lpm_counter:q2_rtl_0 " "Info: Elaborated megafunction instantiation \"cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"cnt10:u3\|lpm_counter:q2_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/lpm_counter.tdf" 432 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "qiangda:u2\|q\[0\] " "Warning: Latch qiangda:u2\|q\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal data\[1\]" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "qiangda:u2\|q\[1\] " "Warning: Latch qiangda:u2\|q\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal data\[0\]" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "qiangda:u2\|q\[2\] " "Warning: Latch qiangda:u2\|q\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal data\[0\]" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "qiangda:u2\|q\[3\] " "Warning: Latch qiangda:u2\|q\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal data\[1\]" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "qiangda:u2\|cout " "Warning: Latch qiangda:u2\|cout has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA data\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal data\[4\]" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 12 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "87 " "Info: Implemented 87 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "58 " "Info: Implemented 58 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "174 " "Info: Peak virtual memory: 174 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 10 00:49:36 2008 " "Info: Processing ended: Thu Jul 10 00:49:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:31 " "Info: Elapsed time: 00:01:31" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}