?? prev_cmp_qiangdaqi.tan.qmsg
字號:
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "qiangda:u2\|cout " "Warning: Node \"qiangda:u2\|cout\" is a latch" { } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qiangda:u2\|q\[0\] " "Warning: Node \"qiangda:u2\|q\[0\]\" is a latch" { } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qiangda:u2\|q\[1\] " "Warning: Node \"qiangda:u2\|q\[1\]\" is a latch" { } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qiangda:u2\|q\[2\] " "Warning: Node \"qiangda:u2\|q\[2\]\" is a latch" { } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qiangda:u2\|q\[3\] " "Warning: Node \"qiangda:u2\|q\[3\]\" is a latch" { } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 0}
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