{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "data\[4\] register cnt10:u3\|q1\[1\] register cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 100.0 MHz 10.0 ns Internal " "Info: Clock \"data\[4\]\" has Internal fmax of 100.0 MHz between source register \"cnt10:u3\|q1\[1\]\" and destination register \"cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest register register " "Info: + Longest register to register delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt10:u3\|q1\[1\] 1 REG LC3_E2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_E2; Fanout = 6; REG Node = 'cnt10:u3\|q1\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt10:u3|q1[1] } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 2.000 ns cnt10:u3\|Equal1~30 2 COMB LC2_E2 2 " "Info: 2: + IC(0.300 ns) + CELL(1.700 ns) = 2.000 ns; Loc. = LC2_E2; Fanout = 2; COMB Node = 'cnt10:u3\|Equal1~30'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { cnt10:u3|q1[1] cnt10:u3|Equal1~30 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.400 ns) 4.300 ns cnt10:u3\|process0~0 3 COMB LC1_E1 4 " "Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 4.300 ns; Loc. = LC1_E1; Fanout = 4; COMB Node = 'cnt10:u3\|process0~0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { cnt10:u3|Equal1~30 cnt10:u3|process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 6.200 ns cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~50 4 COMB LC3_E1 7 " "Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 6.200 ns; Loc. = LC3_E1; Fanout = 7; COMB Node = 'cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { cnt10:u3|process0~0 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 7.600 ns cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 5 REG LC6_E1 6 " "Info: 5: + IC(0.300 ns) + CELL(1.100 ns) = 7.600 ns; Loc. = LC6_E1; Fanout = 6; REG Node = 'cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns ( 76.32 % ) " "Info: Total cell delay = 5.800 ns ( 76.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 23.68 % ) " "Info: Total interconnect delay = 1.800 ns ( 23.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { cnt10:u3|q1[1] cnt10:u3|Equal1~30 cnt10:u3|process0~0 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { cnt10:u3|q1[1] {} cnt10:u3|Equal1~30 {} cnt10:u3|process0~0 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.300ns 0.900ns 0.300ns 0.300ns } { 0.000ns 1.700ns 1.400ns 1.600ns 1.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.300 ns - Smallest " "Info: - Smallest clock skew is -1.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "data\[4\] destination 20.700 ns + Shortest register " "Info: + Shortest clock path from clock \"data\[4\]\" to destination register is 20.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns data\[4\] 1 CLK PIN_13 5 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_13; Fanout = 5; CLK Node = 'data\[4\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[4] } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.600 ns) 10.800 ns qiangda:u2\|cout~235 2 COMB LC6_E4 2 " "Info: 2: + IC(4.300 ns) + CELL(1.600 ns) = 10.800 ns; Loc. = LC6_E4; Fanout = 2; COMB Node = 'qiangda:u2\|cout~235'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { data[4] qiangda:u2|cout~235 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 12.700 ns qiangda:u2\|cout~238 3 COMB LC8_E4 1 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 12.700 ns; Loc. = LC8_E4; Fanout = 1; COMB Node = 'qiangda:u2\|cout~238'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { qiangda:u2|cout~235 qiangda:u2|cout~238 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 14.600 ns qiangda:u2\|cout 4 REG LC2_E4 8 " "Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 14.600 ns; Loc. = LC2_E4; Fanout = 8; REG Node = 'qiangda:u2\|cout'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { qiangda:u2|cout~238 qiangda:u2|cout } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 17.200 ns cnt10:u3\|clk1 5 COMB LC1_E3 9 " "Info: 5: + IC(1.000 ns) + CELL(1.600 ns) = 17.200 ns; Loc. = LC1_E3; Fanout = 9; COMB Node = 'cnt10:u3\|clk1'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { qiangda:u2|cout cnt10:u3|clk1 } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 20.700 ns cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 6 REG LC6_E1 6 " "Info: 6: + IC(3.500 ns) + CELL(0.000 ns) = 20.700 ns; Loc. = LC6_E1; Fanout = 6; REG Node = 'cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns ( 54.59 % ) " "Info: Total cell delay = 11.300 ns ( 54.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.400 ns ( 45.41 % ) " "Info: Total interconnect delay = 9.400 ns ( 45.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "20.700 ns" { data[4] qiangda:u2|cout~235 qiangda:u2|cout~238 qiangda:u2|cout cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "20.700 ns" { data[4] {} data[4]~out {} qiangda:u2|cout~235 {} qiangda:u2|cout~238 {} qiangda:u2|cout {} cnt10:u3|clk1 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 4.300ns 0.300ns 0.300ns 1.000ns 3.500ns } { 0.000ns 4.900ns 1.600ns 1.600ns 1.600ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "data\[4\] source 22.000 ns - Longest register " "Info: - Longest clock path from clock \"data\[4\]\" to source register is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns data\[4\] 1 CLK PIN_13 5 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_13; Fanout = 5; CLK Node = 'data\[4\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[4] } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.400 ns) 10.600 ns qiangda:u2\|q\[3\]~255 2 COMB LC4_E4 2 " "Info: 2: + IC(4.300 ns) + CELL(1.400 ns) = 10.600 ns; Loc. = LC4_E4; Fanout = 2; COMB Node = 'qiangda:u2\|q\[3\]~255'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { data[4] qiangda:u2|q[3]~255 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 12.300 ns qiangda:u2\|cout~237 3 COMB LC7_E4 1 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 12.300 ns; Loc. = LC7_E4; Fanout = 1; COMB Node = 'qiangda:u2\|cout~237'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { qiangda:u2|q[3]~255 qiangda:u2|cout~237 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 14.000 ns qiangda:u2\|cout~238 4 COMB LC8_E4 1 " "Info: 4: + IC(0.300 ns) + CELL(1.400 ns) = 14.000 ns; Loc. = LC8_E4; Fanout = 1; COMB Node = 'qiangda:u2\|cout~238'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { qiangda:u2|cout~237 qiangda:u2|cout~238 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 15.900 ns qiangda:u2\|cout 5 REG LC2_E4 8 " "Info: 5: + IC(0.300 ns) + CELL(1.600 ns) = 15.900 ns; Loc. = LC2_E4; Fanout = 8; REG Node = 'qiangda:u2\|cout'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { qiangda:u2|cout~238 qiangda:u2|cout } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 18.500 ns cnt10:u3\|clk1 6 COMB LC1_E3 9 " "Info: 6: + IC(1.000 ns) + CELL(1.600 ns) = 18.500 ns; Loc. = LC1_E3; Fanout = 9; COMB Node = 'cnt10:u3\|clk1'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { qiangda:u2|cout cnt10:u3|clk1 } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 22.000 ns cnt10:u3\|q1\[1\] 7 REG LC3_E2 6 " "Info: 7: + IC(3.500 ns) + CELL(0.000 ns) = 22.000 ns; Loc. = LC3_E2; Fanout = 6; REG Node = 'cnt10:u3\|q1\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.300 ns ( 55.91 % ) " "Info: Total cell delay = 12.300 ns ( 55.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.700 ns ( 44.09 % ) " "Info: Total interconnect delay = 9.700 ns ( 44.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { data[4] qiangda:u2|q[3]~255 qiangda:u2|cout~237 qiangda:u2|cout~238 qiangda:u2|cout cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { data[4] {} data[4]~out {} qiangda:u2|q[3]~255 {} qiangda:u2|cout~237 {} qiangda:u2|cout~238 {} qiangda:u2|cout {} cnt10:u3|clk1 {} cnt10:u3|q1[1] {} } { 0.000ns 0.000ns 4.300ns 0.300ns 0.300ns 0.300ns 1.000ns 3.500ns } { 0.000ns 4.900ns 1.400ns 1.400ns 1.400ns 1.600ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "20.700 ns" { data[4] qiangda:u2|cout~235 qiangda:u2|cout~238 qiangda:u2|cout cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "20.700 ns" { data[4] {} data[4]~out {} qiangda:u2|cout~235 {} qiangda:u2|cout~238 {} qiangda:u2|cout {} cnt10:u3|clk1 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 4.300ns 0.300ns 0.300ns 1.000ns 3.500ns } { 0.000ns 4.900ns 1.600ns 1.600ns 1.600ns 1.600ns 0.000ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { data[4] qiangda:u2|q[3]~255 qiangda:u2|cout~237 qiangda:u2|cout~238 qiangda:u2|cout cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { data[4] {} data[4]~out {} qiangda:u2|q[3]~255 {} qiangda:u2|cout~237 {} qiangda:u2|cout~238 {} qiangda:u2|cout {} cnt10:u3|clk1 {} cnt10:u3|q1[1] {} } { 0.000ns 0.000ns 4.300ns 0.300ns 0.300ns 0.300ns 1.000ns 3.500ns } { 0.000ns 4.900ns 1.400ns 1.400ns 1.400ns 1.600ns 1.600ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { cnt10:u3|q1[1] cnt10:u3|Equal1~30 cnt10:u3|process0~0 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { cnt10:u3|q1[1] {} cnt10:u3|Equal1~30 {} cnt10:u3|process0~0 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.300ns 0.900ns 0.300ns 0.300ns } { 0.000ns 1.700ns 1.400ns 1.600ns 1.100ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "20.700 ns" { data[4] qiangda:u2|cout~235 qiangda:u2|cout~238 qiangda:u2|cout cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "20.700 ns" { data[4] {} data[4]~out {} qiangda:u2|cout~235 {} qiangda:u2|cout~238 {} qiangda:u2|cout {} cnt10:u3|clk1 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 4.300ns 0.300ns 0.300ns 1.000ns 3.500ns } { 0.000ns 4.900ns 1.600ns 1.600ns 1.600ns 1.600ns 0.000ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { data[4] qiangda:u2|q[3]~255 qiangda:u2|cout~237 qiangda:u2|cout~238 qiangda:u2|cout cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { data[4] {} data[4]~out {} qiangda:u2|q[3]~255 {} qiangda:u2|cout~237 {} qiangda:u2|cout~238 {} qiangda:u2|cout {} cnt10:u3|clk1 {} cnt10:u3|q1[1] {} } { 0.000ns 0.000ns 4.300ns 0.300ns 0.300ns 0.300ns 1.000ns 3.500ns } { 0.000ns 4.900ns 1.400ns 1.400ns 1.400ns 1.600ns 1.600ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "data\[5\] register cnt10:u3\|q1\[1\] register cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 97.09 MHz 10.3 ns Internal " "Info: Clock \"data\[5\]\" has Internal fmax of 97.09 MHz between source register \"cnt10:u3\|q1\[1\]\" and destination register \"cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]\" (period= 10.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest register register " "Info: + Longest register to register delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt10:u3\|q1\[1\] 1 REG LC3_E2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_E2; Fanout = 6; REG Node = 'cnt10:u3\|q1\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt10:u3|q1[1] } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 2.000 ns cnt10:u3\|Equal1~30 2 COMB LC2_E2 2 " "Info: 2: + IC(0.300 ns) + CELL(1.700 ns) = 2.000 ns; Loc. = LC2_E2; Fanout = 2; COMB Node = 'cnt10:u3\|Equal1~30'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { cnt10:u3|q1[1] cnt10:u3|Equal1~30 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.400 ns) 4.300 ns cnt10:u3\|process0~0 3 COMB LC1_E1 4 " "Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 4.300 ns; Loc. = LC1_E1; Fanout = 4; COMB Node = 'cnt10:u3\|process0~0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { cnt10:u3|Equal1~30 cnt10:u3|process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 6.200 ns cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~50 4 COMB LC3_E1 7 " "Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 6.200 ns; Loc. = LC3_E1; Fanout = 7; COMB Node = 'cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { cnt10:u3|process0~0 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 7.600 ns cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 5 REG LC6_E1 6 " "Info: 5: + IC(0.300 ns) + CELL(1.100 ns) = 7.600 ns; Loc. = LC6_E1; Fanout = 6; REG Node = 'cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns ( 76.32 % ) " "Info: Total cell delay = 5.800 ns ( 76.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 23.68 % ) " "Info: Total interconnect delay = 1.800 ns ( 23.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { cnt10:u3|q1[1] cnt10:u3|Equal1~30 cnt10:u3|process0~0 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { cnt10:u3|q1[1] {} cnt10:u3|Equal1~30 {} cnt10:u3|process0~0 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.300ns 0.900ns 0.300ns 0.300ns } { 0.000ns 1.700ns 1.400ns 1.600ns 1.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.600 ns - Smallest " "Info: - Smallest clock skew is -1.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "data\[5\] destination 20.600 ns + Shortest register " "Info: + Shortest clock path from clock \"data\[5\]\" to destination register is 20.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns data\[5\] 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'data\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[5] } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.700 ns) 10.900 ns qiangda:u2\|cout~237 2 COMB LC7_E4 1 " "Info: 2: + IC(4.300 ns) + CELL(1.700 ns) = 10.900 ns; Loc. = LC7_E4; Fanout = 1; COMB Node = 'qiangda:u2\|cout~237'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { data[5] qiangda:u2|cout~237 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 12.600 ns qiangda:u2\|cout~238 3 COMB LC8_E4 1 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 12.600 ns; Loc. = LC8_E4; Fanout = 1; COMB Node = 'qiangda:u2\|cout~238'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { qiangda:u2|cout~237 qiangda:u2|cout~238 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 14.500 ns qiangda:u2\|cout 4 REG LC2_E4 8 " "Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 14.500 ns; Loc. = LC2_E4; Fanout = 8; REG Node = 'qiangda:u2\|cout'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { qiangda:u2|cout~238 qiangda:u2|cout } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 17.100 ns cnt10:u3\|clk1 5 COMB LC1_E3 9 " "Info: 5: + IC(1.000 ns) + CELL(1.600 ns) = 17.100 ns; Loc. = LC1_E3; Fanout = 9; COMB Node = 'cnt10:u3\|clk1'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { qiangda:u2|cout cnt10:u3|clk1 } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 20.600 ns cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 6 REG LC6_E1 6 " "Info: 6: + IC(3.500 ns) + CELL(0.000 ns) = 20.600 ns; Loc. = LC6_E1; Fanout = 6; REG Node = 'cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns ( 54.37 % ) " "Info: Total cell delay = 11.200 ns ( 54.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.400 ns ( 45.63 % ) " "Info: Total interconnect delay = 9.400 ns ( 45.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "20.600 ns" { data[5] qiangda:u2|cout~237 qiangda:u2|cout~238 qiangda:u2|cout cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "20.600 ns" { data[5] {} data[5]~out {} qiangda:u2|cout~237 {} qiangda:u2|cout~238 {} qiangda:u2|cout {} cnt10:u3|clk1 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 4.300ns 0.300ns 0.300ns 1.000ns 3.500ns } { 0.000ns 4.900ns 1.700ns 1.400ns 1.600ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "data\[5\] source 22.200 ns - Longest register " "Info: - Longest clock path from clock \"data\[5\]\" to source register is 22.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns data\[5\] 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'data\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[5] } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.600 ns) 10.800 ns qiangda:u2\|q\[3\]~255 2 COMB LC4_E4 2 " "Info: 2: + IC(4.300 ns) + CELL(1.600 ns) = 10.800 ns; Loc. = LC4_E4; Fanout = 2; COMB Node = 'qiangda:u2\|q\[3\]~255'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { data[5] qiangda:u2|q[3]~255 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 12.500 ns qiangda:u2\|cout~237 3 COMB LC7_E4 1 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 12.500 ns; Loc. = LC7_E4; Fanout = 1; COMB Node = 'qiangda:u2\|cout~237'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { qiangda:u2|q[3]~255 qiangda:u2|cout~237 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 14.200 ns qiangda:u2\|cout~238 4 COMB LC8_E4 1 " "Info: 4: + IC(0.300 ns) + CELL(1.400 ns) = 14.200 ns; Loc. = LC8_E4; Fanout = 1; COMB Node = 'qiangda:u2\|cout~238'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { qiangda:u2|cout~237 qiangda:u2|cout~238 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 16.100 ns qiangda:u2\|cout 5 REG LC2_E4 8 " "Info: 5: + IC(0.300 ns) + CELL(1.600 ns) = 16.100 ns; Loc. = LC2_E4; Fanout = 8; REG Node = 'qiangda:u2\|cout'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { qiangda:u2|cout~238 qiangda:u2|cout } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 18.700 ns cnt10:u3\|clk1 6 COMB LC1_E3 9 " "Info: 6: + IC(1.000 ns) + CELL(1.600 ns) = 18.700 ns; Loc. = LC1_E3; Fanout = 9; COMB Node = 'cnt10:u3\|clk1'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { qiangda:u2|cout cnt10:u3|clk1 } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 22.200 ns cnt10:u3\|q1\[1\] 7 REG LC3_E2 6 " "Info: 7: + IC(3.500 ns) + CELL(0.000 ns) = 22.200 ns; Loc. = LC3_E2; Fanout = 6; REG Node = 'cnt10:u3\|q1\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.500 ns ( 56.31 % ) " "Info: Total cell delay = 12.500 ns ( 56.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.700 ns ( 43.69 % ) " "Info: Total interconnect delay = 9.700 ns ( 43.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "22.200 ns" { data[5] qiangda:u2|q[3]~255 qiangda:u2|cout~237 qiangda:u2|cout~238 qiangda:u2|cout cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "22.200 ns" { data[5] {} data[5]~out {} qiangda:u2|q[3]~255 {} qiangda:u2|cout~237 {} qiangda:u2|cout~238 {} qiangda:u2|cout {} cnt10:u3|clk1 {} cnt10:u3|q1[1] {} } { 0.000ns 0.000ns 4.300ns 0.300ns 0.300ns 0.300ns 1.000ns 3.500ns } { 0.000ns 4.900ns 1.600ns 1.400ns 1.400ns 1.600ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "20.600 ns" { data[5] qiangda:u2|cout~237 qiangda:u2|cout~238 qiangda:u2|cout cnt10:u3|clk1 cnt10:u