?? qiangdaqi.sim.rpt
字號:
; |qiangdaqi|cnt10:u3|Mux~133 ; |qiangdaqi|cnt10:u3|Mux~133 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2683 ; |qiangdaqi|qiangda:u2|Mux~2683 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2684 ; |qiangdaqi|qiangda:u2|Mux~2684 ; data_out0 ;
; |qiangdaqi|qiangda:u2|process0~478 ; |qiangdaqi|qiangda:u2|process0~478 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2685 ; |qiangdaqi|qiangda:u2|Mux~2685 ; data_out0 ;
; |qiangdaqi|qiangda:u2|process0~479 ; |qiangdaqi|qiangda:u2|process0~479 ; data_out0 ;
; |qiangdaqi|qiangda:u2|process0~480 ; |qiangdaqi|qiangda:u2|process0~480 ; data_out0 ;
; |qiangdaqi|qiangda:u2|process0~481 ; |qiangdaqi|qiangda:u2|process0~481 ; data_out0 ;
; |qiangdaqi|qiangda:u2|process0~482 ; |qiangdaqi|qiangda:u2|process0~482 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2687 ; |qiangdaqi|qiangda:u2|Mux~2687 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2688 ; |qiangdaqi|qiangda:u2|Mux~2688 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2689 ; |qiangdaqi|qiangda:u2|Mux~2689 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2690 ; |qiangdaqi|qiangda:u2|Mux~2690 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2691 ; |qiangdaqi|qiangda:u2|Mux~2691 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2693 ; |qiangdaqi|qiangda:u2|Mux~2693 ; data_out0 ;
; |qiangdaqi|qiangda:u2|process0~483 ; |qiangdaqi|qiangda:u2|process0~483 ; data_out0 ;
; |qiangdaqi|cnt10:u3|q1[0]~11 ; |qiangdaqi|cnt10:u3|q1[0]~11 ; data_out0 ;
; |qiangdaqi|cnt10:u3|q1[1]~258 ; |qiangdaqi|cnt10:u3|q1[1]~258 ; data_out0 ;
; |qiangdaqi|rtl~14 ; |qiangdaqi|rtl~14 ; data_out0 ;
; |qiangdaqi|cnt10:u3|q1[2]~259 ; |qiangdaqi|cnt10:u3|q1[2]~259 ; data_out0 ;
; |qiangdaqi|rtl~15 ; |qiangdaqi|rtl~15 ; data_out0 ;
; |qiangdaqi|qiangda:u2|cout ; |qiangdaqi|qiangda:u2|cout ; data_out0 ;
; |qiangdaqi|clk2 ; |qiangdaqi|clk2 ; dataout ;
; |qiangdaqi|clk ; |qiangdaqi|clk ; dataout ;
; |qiangdaqi|clr ; |qiangdaqi|clr ; dataout ;
; |qiangdaqi|data[0] ; |qiangdaqi|data[0] ; dataout ;
; |qiangdaqi|data[6] ; |qiangdaqi|data[6] ; dataout ;
; |qiangdaqi|data[2] ; |qiangdaqi|data[2] ; dataout ;
; |qiangdaqi|data[4] ; |qiangdaqi|data[4] ; dataout ;
; |qiangdaqi|data[1] ; |qiangdaqi|data[1] ; dataout ;
; |qiangdaqi|data[5] ; |qiangdaqi|data[5] ; dataout ;
; |qiangdaqi|data[7] ; |qiangdaqi|data[7] ; dataout ;
; |qiangdaqi|data[3] ; |qiangdaqi|data[3] ; dataout ;
; |qiangdaqi|din ; |qiangdaqi|din ; dataout ;
; |qiangdaqi|star ; |qiangdaqi|star ; dataout ;
; |qiangdaqi|sel ; |qiangdaqi|sel ; dataout ;
; |qiangdaqi|ring ; |qiangdaqi|ring ; padio ;
; |qiangdaqi|t3 ; |qiangdaqi|t3 ; padio ;
; |qiangdaqi|t4 ; |qiangdaqi|t4 ; padio ;
; |qiangdaqi|qh[0] ; |qiangdaqi|qh[0] ; padio ;
; |qiangdaqi|qh[1] ; |qiangdaqi|qh[1] ; padio ;
; |qiangdaqi|q1[0] ; |qiangdaqi|q1[0] ; padio ;
; |qiangdaqi|q1[1] ; |qiangdaqi|q1[1] ; padio ;
; |qiangdaqi|q1[2] ; |qiangdaqi|q1[2] ; padio ;
; |qiangdaqi|q1[3] ; |qiangdaqi|q1[3] ; padio ;
; |qiangdaqi|q2[0] ; |qiangdaqi|q2[0] ; padio ;
; |qiangdaqi|q2[1] ; |qiangdaqi|q2[1] ; padio ;
; |qiangdaqi|q2[2] ; |qiangdaqi|q2[2] ; padio ;
; |qiangdaqi|q2[3] ; |qiangdaqi|q2[3] ; padio ;
; |qiangdaqi|q3[0] ; |qiangdaqi|q3[0] ; padio ;
; |qiangdaqi|q3[2] ; |qiangdaqi|q3[2] ; padio ;
; |qiangdaqi|q2[0]~0 ; |qiangdaqi|q2[0]~0 ; data_out0 ;
; |qiangdaqi|q2[1]~1 ; |qiangdaqi|q2[1]~1 ; data_out0 ;
; |qiangdaqi|q2[2]~2 ; |qiangdaqi|q2[2]~2 ; data_out0 ;
; |qiangdaqi|q2[3]~3 ; |qiangdaqi|q2[3]~3 ; data_out0 ;
+-------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+--------------------------------+--------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------+--------------------------------+------------------+
; |qiangdaqi|cnt10:u3|Mux~126 ; |qiangdaqi|cnt10:u3|Mux~126 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2686 ; |qiangdaqi|qiangda:u2|Mux~2686 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2692 ; |qiangdaqi|qiangda:u2|Mux~2692 ; data_out0 ;
; |qiangdaqi|cnt10:u3|Mux~134 ; |qiangdaqi|cnt10:u3|Mux~134 ; data_out0 ;
; |qiangdaqi|cnt10:u3|Mux~135 ; |qiangdaqi|cnt10:u3|Mux~135 ; data_out0 ;
; |qiangdaqi|cnt10:u3|Mux~136 ; |qiangdaqi|cnt10:u3|Mux~136 ; data_out0 ;
; |qiangdaqi|q3[1] ; |qiangdaqi|q3[1] ; padio ;
; |qiangdaqi|q3[3] ; |qiangdaqi|q3[3] ; padio ;
+--------------------------------+--------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+--------------------------------+--------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------+--------------------------------+------------------+
; |qiangdaqi|cnt10:u3|Mux~126 ; |qiangdaqi|cnt10:u3|Mux~126 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2686 ; |qiangdaqi|qiangda:u2|Mux~2686 ; data_out0 ;
; |qiangdaqi|qiangda:u2|Mux~2692 ; |qiangdaqi|qiangda:u2|Mux~2692 ; data_out0 ;
; |qiangdaqi|cnt10:u3|Mux~134 ; |qiangdaqi|cnt10:u3|Mux~134 ; data_out0 ;
; |qiangdaqi|cnt10:u3|Mux~135 ; |qiangdaqi|cnt10:u3|Mux~135 ; data_out0 ;
; |qiangdaqi|cnt10:u3|Mux~136 ; |qiangdaqi|cnt10:u3|Mux~136 ; data_out0 ;
+--------------------------------+--------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Thu Jul 10 14:53:31 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Warning: Found clock high time violation at 411.3 ns on register "|qiangdaqi|cnt10:u3|q1[0]"
Warning: Found clock high time violation at 411.3 ns on register "|qiangdaqi|cnt10:u3|q1[1]"
Warning: Found clock high time violation at 411.3 ns on register "|qiangdaqi|cnt10:u3|q1[2]"
Warning: Found clock high time violation at 411.3 ns on register "|qiangdaqi|cnt10:u3|q1[3]"
Warning: Found clock high time violation at 411.3 ns on register "|qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[0]"
Warning: Found clock high time violation at 411.3 ns on register "|qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1]"
Warning: Found clock high time violation at 411.3 ns on register "|qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[2]"
Warning: Found clock high time violation at 411.3 ns on register "|qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[3]"
Warning: Found clock high time violation at 531.5 ns on register "|qiangdaqi|cnt10:u3|q1[0]"
Warning: Found clock high time violation at 531.5 ns on register "|qiangdaqi|cnt10:u3|q1[1]"
Warning: Found clock high time violation at 531.5 ns on register "|qiangdaqi|cnt10:u3|q1[2]"
Warning: Found clock high time violation at 531.5 ns on register "|qiangdaqi|cnt10:u3|q1[3]"
Warning: Found clock high time violation at 531.5 ns on register "|qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[0]"
Warning: Found clock high time violation at 531.5 ns on register "|qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1]"
Warning: Found clock high time violation at 531.5 ns on register "|qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[2]"
Warning: Found clock high time violation at 531.5 ns on register "|qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[3]"
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 91.30 %
Info: Number of transitions in simulation is 2299
Info: Quartus II Simulator was successful. 0 errors, 16 warnings
Info: Processing ended: Thu Jul 10 14:53:32 2008
Info: Elapsed time: 00:00:02
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -