library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
     port( sel   : in std_logic_vector(1 downto 0);
           q1,q2 : buffer std_logic_vector(3 downto 0);
           clr   : in  std_logic;
           star  : in  std_logic;
           clk   : in  std_logic;
           in0   : in  std_logic;
           clk3  : in  std_logic;
           ring  : out std_logic;
           t3    : buffer std_logic;
           t4    : buffer std_logic;
           din   : in  std_logic);
end;
architecture one of cnt10 is
signal t1     :std_logic;
signal t2     :std_logic;
signal t5     :std_logic;
signal t6     :std_logic;
signal temp   :std_logic;
signal temp2   :std_logic;
signal clk1   :std_logic;
signal ringin :std_logic;

begin
clk1<=clk and (not in0);
process(clk3,star)
    begin
       if rising_edge(clk3) then
       t1<=star;
       t2<=t1;
       end if;
end process;
    temp<=(not t1)and t2;
      process (temp,clr)
         begin 
          if clr='0' then t3<='0'; 
            elsif rising_edge(temp) 
                   then t3<='1';
          end if;     
      end process;  
process(clk1,clr,in0,t3,sel)
 begin
 if clr='0' then 
   ringin<='0';
   case sel is
   when "00"  => q1<="0000";q2<="0011";
   when "01"  => q1<="0000";q2<="0110";
   when "10"  => q1<="0000";q2<="1001";
   when others =>null;
   end case;
  elsif t3 = '1' then 
   if rising_edge(clk1) then
    if (q1="0000" and q2="0000")  then q1<=q1;q2<=q2;ringin<='1';
     elsif   q1="0000" then q1<="1001";q2<=q2-1;            
         else   q1<=q1-1;
      end if;
    end if;
   if in0='1' then ringin<='1'; 
  end if;
end if;         
end process; 
       process(clk3)
       begin
       if rising_edge(clk3) then
       t5<=din;
       t6<=t1;
       end if;
      end process;
       temp2<=(not t5)and t6;
       process (temp2,clr)
         begin 
          if clr='0' then t4<='1';
            elsif rising_edge(temp2) 
                   then t4<='0';
               end if;     
         end process;
     process(ringin,t4)
        begin
        if t4='0' then
          ring<='0';
         elsif ringin='0' then ring<='0';
         else  ring<=clk3;
         end if;
      end process;       
      end one;