C51 COMPILER V7.00 Beta 6  UPSD_XREG                                                       02/19/2003 15:59:28 PAGE 1   


C51 COMPILER V7.00 Beta 6, COMPILATION OF MODULE UPSD_XREG
OBJECT MODULE PLACED IN upsd_xreg.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE upsd_xreg.c LARGE BROWSE DEBUG OBJECTEXTEND

stmt level    source

   1          // Initialization of uPSD I/Os
   2          //
   3          // William Chin for uPSD3234 from ST Microelectronics
   4          // on June 14, 2002
   5          
   6          /*---------------------------------------------------------------------------
   7          Copyright (c) 2002 ST Microelectronics
   8          This example demo code is provided as is and has no warranty,
   9          implied or otherwise.  You are free to use/modify any of the provided
  10          code at your own risk in your applications with the expressed limitation
  11          of liability (see below) so long as your product using the code contains
  12          at least one uPSD products (device).
  13          
  14          LIMITATION OF LIABILITY:   NEITHER STMicroelectronics NOR ITS VENDORS OR 
  15          AGENTS SHALL BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
  16          INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
  17          CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
  18          OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
  19          --------------------------------------------------------------------------*/
  20          
  21          //-- Includes ----------------------------------------------------------------
  22          
  23          #include "general.h"
  24          #include "upsd3200.h"                   // SFRs
  25          #include "upsd_xreg.h"                  // Bit definitions
  26          
  27          //-- Variables ---------------------------------------------------------------
  28          
  29          extern PSD_REGS UPSD_xreg;
  30          
  31          //-- Aliases of bit IOs -------------------------------------------------------
  32          
  33          //this is just for reference
  34          //#define BELL  UPSD_xreg.DATAOUT_B.bits.PB0
  35          
  36          //-- Functions ----------------------------------------------------------------
  37          
  38          void initXREG(void) {
  39   1      
  40   1          /************ VM ************/
  41   1          UPSD_xreg.VM |= 0x80;
  42   1                                             // bit 7 - PIO (1=enable)
  43   1                                             // bit 4 - RD access FLASH (1=enable)
  44   1                                             // bit 3 - RD access EEPROM (1=enable)
  45   1                                             // bit 2 - PSEN access FLASH (1=enable)
  46   1                                             // bit 1 - PSEN access EEPROM (1=enable)
  47   1                                             // bit 0 - PSEN access SRAM (1=enable)
  48   1      
  49   1                                    
  50   1          /****** power management ******/
  51   1          UPSD_xreg.PMMR0=0x38;               // power-on default = 0x00 
  52   1                                              // bit 5 - CLKIN input to MCell (1=off)
  53   1                                              // bit 4 - CLKIN input to PLD array (1=off)
  54   1                                              // bit 3 - PLD turbo mode (ZPSD only) (1=disable)
  55   1                                              // bit 1 - APD unit (1=enable)
C51 COMPILER V7.00 Beta 6  UPSD_XREG                                                       02/19/2003 15:59:28 PAGE 2   

  56   1          
  57   1          UPSD_xreg.PMMR2=0x70;               // power-on default = 0x00 
  58   1                                              // bit 6 - DBE input to PLD array (1=off)
  59   1                                              // bit 5 - ALE input to PLD array (1=off)
  60   1                                              // bit 4 - CNTL2 input to PLD array (1=off)
  61   1                                              // bit 3 - CNTL1 input to PLD array (1=off)
  62   1                                              // bit 2 - CNTL0 input to PLD array (1=off)
  63   1      }
  64          


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =     20    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)