NOTE:     Speed Grade c8 used for analysis
NOTE:     For a 'Custom' memory device, please ensure that your chosen CL is compatible with your clock speed selection
  
 DDR read data capture: DDR Data to DQS strobe edges at capture registers. 
             Setup slack is  2279 ps    associated with pin 'SDRAM_DQ[3]'  ( variation port 'dq(3)', 'input_cell_L[0]')              
             Hold slack is   1305 ps    associated with pin 'SDRAM_DQ[3]'  ( variation port 'dq(11)', 'input_cell_H[0]')              
  
 Read data resynchronisation: Captured data to resync clock at resync registers ('resynched_data').  
             Setup slack is  1849 ps    associated with pin 'SDRAM_DQ[3]'  ( variation port 'dq(11)', 'input_cell_H[0]')                  
             Hold slack is   3702 ps    associated with pin 'SDRAM_DQ[3]'  ( variation port 'dq(3)', 'input_cell_H[0]')              
  
 Read Postamble Enable: Enable-release to DQS strobe postamble period at negative-edge capture registers.  
             Setup slack is  3141 ps    associated with pin 'SDRAM_DQ[3]'  ( variation port 'dq(3)', 'input_cell_H[0]')                  
             Hold slack is    763 ps    associated with pin 'SDRAM_DQ[4]'  ( variation port 'dq(12)', 'input_cell_L[0]')              
  
 Read Postamble Control: Preset-release ('dq_enable_reset') to DQS strobe negative edges at postamble register ('dq_enable').       
             Setup slack is  4356 ps    associated with pin 'SDRAM_DQ[0]'  ( variation port 'dq(8)', 'input_cell_L[0]')                  
             Hold slack is   2189 ps    associated with pin 'SDRAM_DQ[0]'  ( variation port 'dq(0)', 'input_cell_L[0]')