else if (W_valid & R_ctrl_ld)
          if (^(R_dst_regnum) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_test_bench/R_dst_regnum is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk)
    begin
      if (reset_n)
          if (^(d_write) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_test_bench/d_write is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (d_write)
          if (^(d_byteenable) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_test_bench/d_byteenable is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (d_write | d_read)
          if (^(d_address) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_test_bench/d_address is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk)
    begin
      if (reset_n)
          if (^(d_read) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_test_bench/d_read is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk)
    begin
      if (reset_n)
          if (^(i_read) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_test_bench/i_read is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (i_read)
          if (^(i_address) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_test_bench/i_address is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (i_read & ~i_waitrequest)
          if (^(i_readdata) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_test_bench/i_readdata is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (W_valid & R_ctrl_ld)
          if (^(av_ld_data_aligned_unfiltered) === 1'bx)
            begin
              $write("%0d ns: WARNING: cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (W_valid & R_wr_dst_reg)
          if (^(W_wr_data) === 1'bx)
            begin
              $write("%0d ns: WARNING: cpu_test_bench/W_wr_data is 'x'\n", $time);
            end
    end


  
  reg [31:0] trace_handle; // for $fopen
  initial  
  begin
    trace_handle = $fopen("cpu.tr");
    $fwrite(trace_handle, "version 2\nnumThreads 1\n");
  end
  always @(posedge clk)
    begin
      if (~reset_n || (W_valid))
          $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, rf_wr, R_dst_regnum, rf_wr_data, W_alu_result, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0);
    end


  assign D_inst = ((((D_iw_op[5 : 0] == 2))))? 56'h20207273763032 :
    ((((D_iw_op[5 : 0] == 16))))? 56'h20636d706c7469 :
    ((((D_iw_op[5 : 0] == 18))))? 56'h20207273763138 :
    ((((D_iw_op[5 : 0] == 1))))? 56'h20207273763031 :
    ((((D_iw_op[5 : 0] == 26))))? 56'h20207273763236 :
    ((((D_iw_op[5 : 0] == 42))))? 56'h20207273763432 :
    ((((D_iw_op[5 : 0] == 39))))? 56'h20206c6462696f :
    ((((D_iw_op[5 : 0] == 3))))? 56'h2020206c646275 :
    ((((D_iw_op[5 : 0] == 52))))? 56'h2020206f726869 :
    ((((D_iw_op[5 : 0] == 31))))? 56'h20207273763331 :
    ((((D_iw_op[5 : 0] == 14))))? 56'h20202020626765 :
    ((((D_iw_op[5 : 0] == 6))))? 56'h20202020206272 :
    ((((D_iw_op[5 : 0] == 47))))? 56'h20206c6468696f :
    ((((D_iw_op[5 : 0] == 41))))? 56'h20207273763431 :
    ((((D_iw_op[5 : 0] == 19))))? 56'h20207273763139 :
    ((((D_iw_op[5 : 0] == 55))))? 56'h20206c6477696f :
    ((((D_iw_op[5 : 0] == 29))))? 56'h20207273763239 :
    ((((D_iw_op[5 : 0] == 61))))? 56'h20207273763631 :
    ((((D_iw_op[5 : 0] == 5))))? 56'h20202020737462 :
    ((((D_iw_op[5 : 0] == 62))))? 56'h20207273763632 :
    ((((D_iw_op[5 : 0] == 54))))? 56'h202020626c7475 :
    ((((D_iw_op[5 : 0] == 50))))? 56'h20637573746f6d :
    ((((D_iw_op[5 : 0] == 36))))? 56'h2020206d756c69 :
    ((((D_iw_op[5 : 0] == 28))))? 56'h202020786f7269 :
    ((((D_iw_op[5 : 0] == 8))))? 56'h20636d70676569 :
    ((((D_iw_op[5 : 0] == 23))))? 56'h202020206c6477 :
    ((((D_iw_op[5 : 0] == 32))))? 56'h20636d70657169 :
    ((((D_iw_op[5 : 0] == 15))))? 56'h202020206c6468 :
    ((((D_iw_op[5 : 0] == 21))))? 56'h20202020737477 :
    ((((D_iw_op[5 : 0] == 9))))? 56'h20207273763039 :
    ((((D_iw_op[5 : 0] == 24))))? 56'h20636d706e6569 :
    ((((D_iw_op[5 : 0] == 7))))? 56'h202020206c6462 :
    ((((D_iw_op[5 : 0] == 46))))? 56'h20202062676575 :
    ((((D_iw_op[5 : 0] == 53))))? 56'h2020737477696f :
    ((((D_iw_op[5 : 0] == 33))))? 56'h20207273763333 :
    ((((D_iw_op[5 : 0] == 44))))? 56'h2020616e646869 :
    ((((D_iw_op[5 : 0] == 35))))? 56'h206c646275696f :
    ((((D_iw_op[5 : 0] == 34))))? 56'h20207273763334 :
    ((((D_iw_op[5 : 0] == 45))))? 56'h2020737468696f :
    ((((D_iw_op[5 : 0] == 40))))? 56'h636d7067657569 :
    ((((D_iw_op[5 : 0] == 37))))? 56'h2020737462696f :
    ((((D_iw_op[5 : 0] == 12))))? 56'h202020616e6469 :
    ((((D_iw_op[5 : 0] == 4))))? 56'h20202061646469 :
    ((((D_iw_op[5 : 0] == 27))))? 56'h666c7573686461 :
    ((((D_iw_op[5 : 0] == 49))))? 56'h20207273763439 :
    ((((D_iw_op[5 : 0] == 22))))? 56'h20202020626c74 :
    ((((D_iw_op[5 : 0] == 38))))? 56'h20202020626571 :
    ((((D_iw_op[5 : 0] == 20))))? 56'h202020206f7269 :
    ((((D_iw_op[5 : 0] == 48))))? 56'h636d706c747569 :
    ((((D_iw_op[5 : 0] == 60))))? 56'h2020786f726869 :
    ((((D_iw_op[5 : 0] == 56))))? 56'h20207273763536 :
    ((((D_iw_op[5 : 0] == 43))))? 56'h206c646875696f :
    ((((D_iw_op[5 : 0] == 63))))? 56'h20207273763633 :
    ((((D_iw_op[5 : 0] == 30))))? 56'h20202020626e65 :
    ((((D_iw_op[5 : 0] == 57))))? 56'h20207273763537 :
    ((((D_iw_op[5 : 0] == 0))))? 56'h20202063616c6c :
    ((((D_iw_op[5 : 0] == 11))))? 56'h2020206c646875 :
    ((((D_iw_op[5 : 0] == 59))))? 56'h20666c75736864 :
    ((((D_iw_op[5 : 0] == 51))))? 56'h2020696e697464 :
    ((((D_iw_op[5 : 0] == 10))))? 56'h20207273763130 :
    ((((D_iw_op[5 : 0] == 17))))? 56'h20207273763137 :
    ((((D_iw_op[5 : 0] == 13))))? 56'h20202020737468 :
    ((((D_iw_op[5 : 0] == 25))))? 56'h20207273763235 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 12))))? 56'h20666c75736869 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 7))))? 56'h206d756c787575 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 33))))? 56'h20727376783333 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 46))))? 56'h2020777263746c :
    (((D_op_opx & (D_iw_opx[5 : 0] == 2))))? 56'h202020726f6c69 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 61))))? 56'h202020696e7472 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 43))))? 56'h20727376783433 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 27))))? 56'h2020202073726c :
    (((D_op_opx & (D_iw_opx[5 : 0] == 45))))? 56'h20202074726170 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 17))))? 56'h20727376783137 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 52))))? 56'h2020627265616b :
    (((D_op_opx & (D_iw_opx[5 : 0] == 38))))? 56'h2020726463746c :
    (((D_op_opx & (D_iw_opx[5 : 0] == 48))))? 56'h20636d706c7475 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 29))))? 56'h202063616c6c72 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 8))))? 56'h2020636d706765 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 47))))? 56'h20727376783437 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 14))))? 56'h20202020616e64 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 0))))? 56'h20727376783030 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 56))))? 56'h20727376783536 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 53))))? 56'h2068627265616b :
    (((D_op_opx & (D_iw_opx[5 : 0] == 4))))? 56'h20666c75736870 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 6))))? 56'h202020206e6f72 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 50))))? 56'h20727376783530 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 41))))? 56'h2020696e697469 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 58))))? 56'h20202073726169 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 54))))? 56'h20202073796e63 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 15))))? 56'h20727376783135 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 55))))? 56'h20727376783535 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 62))))? 56'h20202063727374 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 42))))? 56'h20727376783432 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 30))))? 56'h20202020786f72 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 34))))? 56'h20727376783334 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 31))))? 56'h206d756c787373 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 51))))? 56'h20727376783531 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 10))))? 56'h20727376783130 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 1))))? 56'h20202065726574 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 25))))? 56'h20727376783235 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 13))))? 56'h202020206a6d70 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 22))))? 56'h20202020206f72 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 35))))? 56'h20727376783335 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 59))))? 56'h20202020737261 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 20))))? 56'h20727376783230 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 18))))? 56'h202020736c6c69 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 23))))? 56'h206d756c787375 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 21))))? 56'h20727376783231 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 11))))? 56'h20202020726f72 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 26))))? 56'h20202073726c69 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 19))))? 56'h20202020736c6c :
    (((D_op_opx & (D_iw_opx[5 : 0] == 37))))? 56'h20202020646976 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 16))))? 56'h2020636d706c74 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 49))))? 56'h20202020616464 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 44))))? 56'h20727376783434 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 9))))? 56'h20202062726574 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 60))))? 56'h20727376783630 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 63))))? 56'h20727376783633 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 39))))? 56'h202020206d756c :
    (((D_op_opx & (D_iw_opx[5 : 0] == 40))))? 56'h20636d70676575 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 24))))? 56'h2020636d706e65 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 32))))? 56'h2020636d706571 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 5))))? 56'h20202020726574 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 3))))? 56'h20202020726f6c :
    (((D_op_opx & (D_iw_opx[5 : 0] == 57))))? 56'h20202020737562 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 28))))? 56'h206e6578747063 :
    (((D_op_opx & (D_iw_opx[5 : 0] == 36))))? 56'h20202064697675 :
    56'h20202020424144;

  assign W_vinst = W_valid ? D_inst : {7{8'h2d}};

//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  
//  assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off

endmodule