doing_rd_pipe <= 0;
      else 
        //shift bits up
        doing_rd_pipe <= {doing_rd_pipe[1 : 0], doing_rd};

    end


  //It's safe to clock from falling edge of clk to postamble_clk, so use falling edge clock
  always @(negedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          doing_rd_delayed <= 1'b0;
      else 
        doing_rd_delayed <= doing_rd_pipe[1];
    end


  //This copes with DQS mode
  assign dqs_postamble_clk = dq_capture_clk;

  //-----------------------------------------------------------------------------
  //Decide which clock to use for capturing the DQ data
  //-----------------------------------------------------------------------------
  //Use DQS to capture DQ read data
  assign dq_capture_clk = ~wire_dqs_clkctrl_outclk;

  //-----------------------------------------------------------------------------
  //DQ pins and their logic
  //-----------------------------------------------------------------------------
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dq_oe <= 1'b0;
      else 
        dq_oe <= doing_wr;
    end


  //-----------------------------------------------------------------------------
  //Write data registers
  //These are the last registers before the registers in the altddio_bidir. They
  //are clocked off the system clock but feed registers which are clocked off the
  //write clock, so their output is the beginning of 3/4 cycle path.
  //-----------------------------------------------------------------------------
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          wdata_r <= 0;
      else if (wdata_valid)
          //don't latch in data unless it's valid
          wdata_r <= wdata;

    end


  //Concatenate the rising and falling edge data to make a single bus
  assign dq_captured_0 = {dq_captured_falling, dq_captured_rising};

  assign #3125 dq_captured_1 = dq_captured_0;
  //Apply delays in 2 chunks to avoid having to use transport delays
  assign #3125 delayed_dq_captured = dq_captured_1;

  //-----------------------------------------------------------------------------
  //Resynchronisation registers
  //These registers resychronise the captured read data from the DQS clock
  //domain back into an internal PLL clock domain. 
  //-----------------------------------------------------------------------------
  //Use a falling edge for resynch
  always @(negedge resynch_clk or negedge reset_n)
    begin
      if (reset_n == 0)
          resynched_data <= 0;
      else 
        resynched_data <= delayed_dq_captured;
    end


  //don't insert pipeline registers
  assign inter_rdata = resynched_data;

  //-----------------------------------------------------------------------------
  //Pipeline read data registers
  //These optional registers can be inserted to make it easier to meet timing
  //coming out of the local_rdata port of the core. It's especially necessary
  //if a falling edge resynch edge is being used..
  //Note that the rdata_valid signal is also pipelined if this is set.
  //-----------------------------------------------------------------------------

  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          rdata <= 0;
      else 
        rdata <= inter_rdata;
    end



//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  cycloneii_clkctrl dqs_clkctrl
    (
      .clkselect (2'b00),
      .ena (1'b1),
      .inclk (delayed_dqs),
      .outclk (wire_dqs_clkctrl_outclk)
    );

  defparam dqs_clkctrl.ena_register_mode = "none",
           dqs_clkctrl.lpm_type = "cycloneii_clkctrl";

  altddio_bidir \g_dq_io:0:dq_io 
    (
      .aclr (reset),
      .aset (),
      .combout (),
      .datain_h (wdata_r[0]),
      .datain_l (wdata_r[8]),
      .dataout_h (dq_captured_falling[0]),
      .dataout_l (dq_captured_rising[0]),
      .dqsundelayedout (),
      .inclock (dq_capture_clk),
      .inclocken (1'b1),
      .oe (dq_oe),
      .outclock (write_clk),
      .outclocken (1'b1),
      .padio (ddr_dq[0])
    );

  defparam \g_dq_io:0:dq_io .extend_oe_disable = "UNUSED",
           \g_dq_io:0:dq_io .implement_input_in_lcell = "UNUSED",
           \g_dq_io:0:dq_io .intended_device_family = "Cyclone II",
           \g_dq_io:0:dq_io .invert_output = "OFF",
           \g_dq_io:0:dq_io .lpm_hint = "UNUSED",
           \g_dq_io:0:dq_io .lpm_type = "altddio_bidir",
           \g_dq_io:0:dq_io .oe_reg = "REGISTERED",
           \g_dq_io:0:dq_io .power_up_high = "OFF",
           \g_dq_io:0:dq_io .width = 1;

  altddio_bidir \g_dq_io:1:dq_io 
    (
      .aclr (reset),
      .aset (),
      .combout (),
      .datain_h (wdata_r[1]),
      .datain_l (wdata_r[9]),
      .dataout_h (dq_captured_falling[1]),
      .dataout_l (dq_captured_rising[1]),
      .dqsundelayedout (),
      .inclock (dq_capture_clk),
      .inclocken (1'b1),
      .oe (dq_oe),
      .outclock (write_clk),
      .outclocken (1'b1),
      .padio (ddr_dq[1])
    );

  defparam \g_dq_io:1:dq_io .extend_oe_disable = "UNUSED",
           \g_dq_io:1:dq_io .implement_input_in_lcell = "UNUSED",
           \g_dq_io:1:dq_io .intended_device_family = "Cyclone II",
           \g_dq_io:1:dq_io .invert_output = "OFF",
           \g_dq_io:1:dq_io .lpm_hint = "UNUSED",
           \g_dq_io:1:dq_io .lpm_type = "altddio_bidir",
           \g_dq_io:1:dq_io .oe_reg = "REGISTERED",
           \g_dq_io:1:dq_io .power_up_high = "OFF",
           \g_dq_io:1:dq_io .width = 1;

  altddio_bidir \g_dq_io:2:dq_io 
    (
      .aclr (reset),
      .aset (),
      .combout (),
      .datain_h (wdata_r[2]),
      .datain_l (wdata_r[10]),
      .dataout_h (dq_captured_falling[2]),
      .dataout_l (dq_captured_rising[2]),
      .dqsundelayedout (),
      .inclock (dq_capture_clk),
      .inclocken (1'b1),
      .oe (dq_oe),
      .outclock (write_clk),
      .outclocken (1'b1),
      .padio (ddr_dq[2])
    );

  defparam \g_dq_io:2:dq_io .extend_oe_disable = "UNUSED",
           \g_dq_io:2:dq_io .implement_input_in_lcell = "UNUSED",
           \g_dq_io:2:dq_io .intended_device_family = "Cyclone II",
           \g_dq_io:2:dq_io .invert_output = "OFF",
           \g_dq_io:2:dq_io .lpm_hint = "UNUSED",
           \g_dq_io:2:dq_io .lpm_type = "altddio_bidir",
           \g_dq_io:2:dq_io .oe_reg = "REGISTERED",
           \g_dq_io:2:dq_io .power_up_high = "OFF",
           \g_dq_io:2:dq_io .width = 1;

  altddio_bidir \g_dq_io:3:dq_io 
    (
      .aclr (reset),
      .aset (),
      .combout (),
      .datain_h (wdata_r[3]),
      .datain_l (wdata_r[11]),
      .dataout_h (dq_captured_falling[3]),
      .dataout_l (dq_captured_rising[3]),
      .dqsundelayedout (),
      .inclock (dq_capture_clk),
      .inclocken (1'b1),
      .oe (dq_oe),
      .outclock (write_clk),
      .outclocken (1'b1),
      .padio (ddr_dq[3])
    );

  defparam \g_dq_io:3:dq_io .extend_oe_disable = "UNUSED",
           \g_dq_io:3:dq_io .implement_input_in_lcell = "UNUSED",
           \g_dq_io:3:dq_io .intended_device_family = "Cyclone II",
           \g_dq_io:3:dq_io .invert_output = "OFF",
           \g_dq_io:3:dq_io .lpm_hint = "UNUSED",
           \g_dq_io:3:dq_io .lpm_type = "altddio_bidir",
           \g_dq_io:3:dq_io .oe_reg = "REGISTERED",
           \g_dq_io:3:dq_io .power_up_high = "OFF",
           \g_dq_io:3:dq_io .width = 1;

  altddio_bidir \g_dq_io:4:dq_io 
    (
      .aclr (reset),
      .aset (),
      .combout (),
      .datain_h (wdata_r[4]),
      .datain_l (wdata_r[12]),
      .dataout_h (dq_captured_falling[4]),
      .dataout_l (dq_captured_rising[4]),
      .dqsundelayedout (),
      .inclock (dq_capture_clk),
      .inclocken (1'b1),
      .oe (dq_oe),
      .outclock (write_clk),
      .outclocken (1'b1),
      .padio (ddr_dq[4])
    );

  defparam \g_dq_io:4:dq_io .extend_oe_disable = "UNUSED",
           \g_dq_io:4:dq_io .implement_input_in_lcell = "UNUSED",
           \g_dq_io:4:dq_io .intended_device_family = "Cyclone II",
           \g_dq_io:4:dq_io .invert_output = "OFF",
           \g_dq_io:4:dq_io .lpm_hint = "UNUSED",
           \g_dq_io:4:dq_io .lpm_type = "altddio_bidir",
           \g_dq_io:4:dq_io .oe_reg = "REGISTERED",
           \g_dq_io:4:dq_io .power_up_high = "OFF",
           \g_dq_io:4:dq_io .width = 1;

  altddio_bidir \g_dq_io:5:dq_io 
    (
      .aclr (reset),
      .aset (),
      .combout (),
      .datain_h (wdata_r[5]),
      .datain_l (wdata_r[13]),
      .dataout_h (dq_captured_falling[5]),
      .dataout_l (dq_captured_rising[5]),
      .dqsundelayedout (),
      .inclock (dq_capture_clk),
      .inclocken (1'b1),
      .oe (dq_oe),
      .outclock (write_clk),
      .outclocken (1'b1),
      .padio (ddr_dq[5])
    );

  defparam \g_dq_io:5:dq_io .extend_oe_disable = "UNUSED",
           \g_dq_io:5:dq_io .implement_input_in_lcell = "UNUSED",
           \g_dq_io:5:dq_io .intended_device_family = "Cyclone II",
           \g_dq_io:5:dq_io .invert_output = "OFF",
           \g_dq_io:5:dq_io .lpm_hint = "UNUSED",
           \g_dq_io:5:dq_io .lpm_type = "altddio_bidir",
           \g_dq_io:5:dq_io .oe_reg = "REGISTERED",
           \g_dq_io:5:dq_io .power_up_high = "OFF",
           \g_dq_io:5:dq_io .width = 1;

  altddio_bidir \g_dq_io:6:dq_io 
    (
      .aclr (reset),
      .aset (),
      .combout (),
      .datain_h (wdata_r[6]),
      .datain_l (wdata_r[14]),
      .dataout_h (dq_captured_falling[6]),
      .dataout_l (dq_captured_rising[6]),
      .dqsundelayedout (),
      .inclock (dq_capture_clk),