Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Jul 03 16:01:43 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SmallCore -c SmallCore
Info: Selected device EP2C35F672C8 for design "SmallCore"
Info: Implemented PLL "pll:inst|altpll:altpll_component|pll" as Cyclone II PLL type
    Info: Implementing clock multiplication of 8, clock division of 5, and phase shift of 0 degrees (0 ps) for pll:inst|altpll:altpll_component|_clk0 port
    Info: Implementing clock multiplication of 8, clock division of 5, and phase shift of 270 degrees (9375 ps) for pll:inst|altpll:altpll_component|_clk1 port
Info: Fitter is performing a Fast Fit compilation, which decreases Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C35F672I8 is compatible
    Info: Device EP2C50F672C8 is compatible
    Info: Device EP2C50F672I8 is compatible
    Info: Device EP2C70F672C8 is compatible
    Info: Device EP2C70F672I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location E3
    Info: Pin ~nCSO~ is reserved at location D3
    Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Design contains 2 DQS I/Os
Info: Design contains 16 DQ I/Os
Info: Automatically promoted node nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|combout[0] (placed in PIN N23 (LVDS126p, DPCLK7/DQS0R/CQ1R))
    Info: Automatically promoted nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dqs_clkctrl to use location or clock signal Global Clock CLKCTRL_G4
Info: Automatically promoted node nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|combout[0] (placed in PIN G25 (LVDS112p, CDPCLK5/DQS2R/CQ3R))
    Info: Automatically promoted nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dqs_clkctrl to use location or clock signal Global Clock CLKCTRL_G6
Info: Automatically promoted node pll:inst|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_3)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11
Info: Automatically promoted node pll:inst|altpll:altpll_component|_clk1 (placed in counter C1 of PLL_3)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G10
Info: Automatically promoted node SYS_CLK (placed in PIN B13 (CLK8, LVDSCLK4n, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
Info: Automatically promoted node altera_internal_jtag~TCKUTAP 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node altera_internal_jtag~UPDATEUSER 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir~112
        Info: Destination node nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr~99
Info: Automatically promoted node SYS_nRST (placed in PIN AC13 (CLK15, LVDSCLK7p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node nios2e_2C35:inst1|reset_n_sources~19
Info: Automatically promoted node nios2e_2C35:inst1|nios2e_2C35_reset_clk_domain_synch_module:nios2e_2C35_reset_clk_domain_synch|data_out 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|jtag_break~47
        Info: Destination node nios2e_2C35:inst1|cpu:the_cpu|W_rf_wren_a
        Info: Destination node nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_init:\g_ddr_init:init_block|init_addr[8]~78
        Info: Destination node nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetlatch~183
Info: Automatically promoted node sld_hub:sld_hub_inst|node_clrn 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[1]~717
        Info: Destination node nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetlatch~182
        Info: Destination node nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetlatch~183
Info: Automatically promoted node sld_hub:sld_hub_inst|CLR_SIGNAL 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_hub:sld_hub_inst|node_clrn
Info: Automatically promoted node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~406
        Info: Destination node sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5