?? nios2e_2c35.ptf
字號:
format = "Logic";
name = "F_pcb_nxt";
radix = "hexadecimal";
}
SIGNAL aaq
{
format = "Logic";
name = "F_pcb";
radix = "hexadecimal";
}
SIGNAL aar
{
format = "Logic";
name = "F_vinst";
radix = "ascii";
}
SIGNAL aas
{
format = "Logic";
name = "D_vinst";
radix = "ascii";
}
SIGNAL aat
{
format = "Logic";
name = "R_vinst";
radix = "ascii";
}
SIGNAL aau
{
format = "Logic";
name = "E_vinst";
radix = "ascii";
}
SIGNAL aav
{
format = "Logic";
name = "W_vinst";
radix = "ascii";
}
SIGNAL aaw
{
format = "Logic";
name = "F_valid";
radix = "hexadecimal";
}
SIGNAL aax
{
format = "Logic";
name = "D_valid";
radix = "hexadecimal";
}
SIGNAL aay
{
format = "Logic";
name = "R_valid";
radix = "hexadecimal";
}
SIGNAL aaz
{
format = "Logic";
name = "E_valid";
radix = "hexadecimal";
}
SIGNAL aba
{
format = "Logic";
name = "W_valid";
radix = "hexadecimal";
}
SIGNAL abb
{
format = "Logic";
name = "D_wr_dst_reg";
radix = "hexadecimal";
}
SIGNAL abc
{
format = "Logic";
name = "D_dst_regnum";
radix = "hexadecimal";
}
SIGNAL abd
{
format = "Logic";
name = "W_wr_data";
radix = "hexadecimal";
}
SIGNAL abe
{
format = "Logic";
name = "F_iw";
radix = "hexadecimal";
}
SIGNAL abf
{
format = "Logic";
name = "D_iw";
radix = "hexadecimal";
}
SIGNAL abg
{
format = "Divider";
name = "breaks";
radix = "";
}
SIGNAL abh
{
format = "Logic";
name = "hbreak_req";
radix = "hexadecimal";
}
SIGNAL abi
{
format = "Logic";
name = "oci_hbreak_req";
radix = "hexadecimal";
}
SIGNAL abj
{
format = "Logic";
name = "hbreak_enabled";
radix = "hexadecimal";
}
SIGNAL abk
{
format = "Logic";
name = "wait_for_one_post_bret_inst";
radix = "hexadecimal";
}
}
}
}
MODULE sys_clk_timer
{
class = "altera_avalon_timer";
class_version = "7.0";
iss_model_name = "altera_avalon_timer";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "0";
}
Base_Address = "0x00000800";
Address_Group = "0";
}
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "3";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "Timer with 20 ms timeout period.";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "20";
period_units = "ms";
reset_output = "0";
timeout_pulse_output = "0";
mult = "0.001";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk_timer.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE led_pio
{
class = "altera_avalon_pio";
class_version = "7.0";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "8";
}
PORT out_port
{
direction = "output";
Is_Enabled = "1";
width = "8";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "8";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "8";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "8";
Base_Address = "0x00000820";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Is_Readable = "0";
Is_Writable = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
}
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 8-bit PIO using <br>
output pins";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE sysid
{
class = "altera_avalon_sysid";
class_version = "7.0";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "32";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "1";
Data_Width = "32";
Base_Address = "0x00000830";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Read_Latency = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
Address_Group = "0";
IRQ_MASTER cpu/data_master
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