?? nios2e_2c35.ptf
字號:
Write_Wait_States = "peripheral_controlled";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bus_Master = "0";
Bus_Type = "avalon";
Has_IRQ = "0";
Has_Base_Address = "1";
Maximum_Pending_Read_Transactions = "16";
Setup_Time = "0";
Hold_Time = "0";
Is_Memory_Device = "1";
Uses_Tri_State_Data_Bus = "0";
Maximum_Burst_Size = "1";
Linewrap_Bursts = "1";
Interleave_Bursts = "0";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
Base_Address = "0x01000000";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
PORT_WIRING
{
PORT write_clk
{
type = "export";
direction = "input";
width = "1";
}
PORT clk
{
type = "clk";
direction = "input";
width = "1";
}
PORT reset_n
{
type = "reset_n";
direction = "input";
width = "1";
}
PORT local_read_req
{
type = "read";
direction = "input";
width = "1";
}
PORT local_write_req
{
type = "write";
direction = "input";
width = "1";
}
PORT local_addr
{
type = "address";
direction = "input";
width = "22";
}
PORT local_wdata
{
type = "writedata";
direction = "input";
width = "32";
}
PORT local_be
{
type = "byteenable";
direction = "input";
width = "4";
}
PORT local_ready
{
type = "waitrequest_n";
direction = "output";
width = "1";
}
PORT local_rdata
{
type = "readdata";
direction = "output";
width = "32";
}
PORT local_rdata_valid
{
type = "readdatavalid";
direction = "output";
width = "1";
}
PORT clk_to_sdram
{
type = "export";
direction = "output";
width = "1";
}
PORT clk_to_sdram_n
{
type = "export";
direction = "output";
width = "1";
}
PORT ddr_cs_n
{
type = "export";
direction = "output";
width = "1";
}
PORT ddr_cke
{
type = "export";
direction = "output";
width = "1";
}
PORT ddr_a
{
type = "export";
direction = "output";
width = "12";
}
PORT ddr_ba
{
type = "export";
direction = "output";
width = "2";
}
PORT ddr_ras_n
{
type = "export";
direction = "output";
width = "1";
}
PORT ddr_cas_n
{
type = "export";
direction = "output";
width = "1";
}
PORT ddr_we_n
{
type = "export";
direction = "output";
width = "1";
}
PORT ddr_dq
{
type = "export";
direction = "inout";
width = "16";
}
PORT ddr_dqs
{
type = "export";
direction = "inout";
width = "2";
}
PORT ddr_dm
{
type = "export";
direction = "output";
width = "2";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
MEGACORE
{
title = "DDR SDRAM Controller";
version = "7.0";
build = "1";
iptb_version = "v1.3.0 build70";
format_version = "120";
NETLIST_SECTION
{
class = "altera.ipbu.flowbase.netlist.model.DDRSDRAMModel";
active_core = "ddr_sdram_auk_ddr_sdram";
STATIC_SECTION
{
PRIVATES
{
NAMESPACE parameterization
{
PRIVATE use_mem
{
value = "1";
type = "BOOLEAN";
enable = "1";
}
PRIVATE gMEM_TYPE
{
value = "ddr_sdram";
type = "STRING";
enable = "1";
}
PRIVATE projectname
{
value = "SmallCore";
type = "STRING";
enable = "1";
}
PRIVATE ddio_memory_clocks
{
value = "0";
type = "BOOLEAN";
enable = "0";
}
PRIVATE new_wizard
{
value = "false";
type = "STRING";
enable = "1";
}
PRIVATE local_burst_length
{
value = "1";
type = "INTEGER";
enable = "1";
}
PRIVATE burst_length
{
value = "2";
type = "INTEGER";
enable = "1";
}
PRIVATE odt_setting
{
value = "Disabled";
type = "STRING";
enable = "0";
}
PRIVATE chip_selects_per_dimm
{
value = "1";
type = "INTEGER";
enable = "0";
}
PRIVATE mig_device
{
value = "NONE";
type = "STRING";
enable = "1";
}
PRIVATE mig_package
{
value = "NONE";
type = "STRING";
enable = "1";
}
PRIVATE mig_speed_grade
{
value = "NONE";
type = "STRING";
enable = "1";
}
PRIVATE mig_family
{
value = "NONE";
type = "STRING";
enable = "1";
}
PRIVATE mig_defaultByteGroups
{
value = "default_value";
type = "STRING";
enable = "1";
}
PRIVATE mig_ByteGroups
{
value = "default_value";
type = "STRING";
enable = "1";
}
PRIVATE ADVANCED
{
value = "0";
type = "BOOLEAN";
enable = "1";
}
PRIVATE include_x4_dm_pins
{
value = "1";
type = "BOOLEAN";
enable = "0";
}
PRIVATE chipselects
{
value = "1";
type = "INTEGER";
enable = "1";
}
PRIVATE LOCAL_WIDTH
{
value = "32";
type = "INTEGER";
enable = "1";
}
PRIVATE bankbits
{
value = "2";
type = "INTEGER";
enable = "0";
}
PRIVATE width
{
value = "16";
type = "INTEGER";
enable = "1";
}
PRIVATE colbits
{
value = "9";
type = "INTEGER";
enable = "1";
}
PRIVATE rowbits
{
value = "12";
type = "INTEGER";
enable = "1";
}
PRIVATE dq_per_dqs
{
value = "8";
type = "INTEGER";
enable = "0";
}
PRIVATE pch_bit
{
value = "10";
type = "INTEGER";
enable = "1";
}
PRIVATE migratable_bytegroups
{
value = "0";
type = "BOOLEAN";
enable = "0";
}
PRIVATE reg_dimm
{
value = "0";
type = "BOOLEAN";
enable = "1";
}
PRIVATE pipeline_commands
{
value = "1";
type = "BOOLEAN";
enable = "1";
}
PRIVATE enable_resynch_clk
{
value = "1";
type = "BOOLEAN";
enable = "1";
}
PRIVATE enable_capture_clk
{
value = "0";
type = "BOOLEAN";
enable = "0";
}
PRIVATE obj_hierarchy_path
{
value = "Automatically extracted by Quartus synthesis";
type = "STRING";
enable = "0";
}
PRIVATE clock_pin_positive
{
value = "SDRAM_CLK";
type = "STRING";
enable = "1";
}
PRIVATE clock_pin_negative
{
value = "SDRAM_nCLK";
type = "STRING";
enable = "1";
}
PRIVATE clock_fed_back_input
{
value = "fedback_clk_in";
type = "STRING";
enable = "0";
}
PRIVATE run_add_constraints
{
value = "1";
type = "BOOLEAN";
enable = "1";
}
PRIVATE run_verify_timing
{
value = "1";
type = "BOOLEAN";
enable = "1";
}
PRIVATE generate_pll
{
value = "0";
type = "BOOLEAN";
enable = "1";
}
PRIVATE update_top_level
{
value = "0";
type = "BOOLEAN";
enable = "1";
}
PRIVATE manual_hierarchy_control
{
value = "0";
type = "BOOLEAN";
enable = "1";
}
PRIVATE fed_back_clock
{
value = "0";
type = "BOOLEAN";
enable = "0";
}
PRIVATE extra_pipeline_regs
{
value = "0";
type = "BOOLEAN";
enable = "1";
}
PRIVATE pipeline_readdata
{
value = "Auto?? 快捷鍵說明
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