; *******************************************************
; * NAME    : INIT.S									*
; * Version : 28.May.2003								* 
; * Description:										*
; *	C start up codes									*
; *	Configure memory, Initialize ISR ,stacks			*
; *	Initialize C-variables								*
; *	Fill zeros into zero-initialized C-variables		*
; *******************************************************
 
    GET ..\inc\memcfg.inc
    GET ..\inc\miscel.inc
;Memory Area
;GCS6 64M 16bit(8MB) SDRAM(0xc000000-0xc7fffff)
;APP    RAM=0xc000000~0xc7effff 
;44BMON RAM=0xc7f0000-0xc7fffff
;STACK	   =0xc7ffa00		   


    IMPORT	|Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
    IMPORT	|Image$$RW$$Base|   ; Base of RAM to initialise
    IMPORT	|Image$$ZI$$Base|   ; Base and limit of area
    IMPORT	|Image$$ZI$$Limit|  ; to zero initialise
   
    
    IMPORT	bios_main
    
    CODE32   ;for start-up code for Thumb mode
    
    AREA    Init,CODE,READONLY
    ENTRY
    
    b ResetHandler	;for debug				
    b HandlerUndef  ;handlerUndef			
    b HandlerSWI	;SWI interrupt handler	
;    b HandlerPabort ;handlerPAbort			
;    b HandlerDabort ;handlerDAbort			
;    b .				;handlerReserved		
;    b HandlerIRQ    ;handlerIRQ				
;    b HandlerFIQ    ;handlerFIQ  

HandlerSWI
    movs pc,r14
HandlerUndef    
    movs pc,r14

;****************************************************
;*	START											*
;****************************************************

ResetHandler

	ldr	    r0,=WTCON	    ;watch dog disable 
    ldr	    r1,=0x0 		
    str	    r1,[r0]

    ldr	    r0,=INTMSK
    ldr	    r1,=0x07ffffff  ;all interrupt disable
    str	    r1,[r0]

    ;****************************************************
    ;*	Set clock control registers						*
    ;****************************************************
    ldr	    r0,=LOCKTIME
    ldr	    r1,=0xfff
    str	    r1,[r0]

	ldr	    r0,=PLLCON							;temporary setting of PLL
	ldr	    r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV)	;Fin=12MHz,Fout=60MHz
	str	    r1,[r0]

    ldr	    r0,=CLKCON		 
    ldr	    r1,=0x7ff8	    					;All unit block CLK enable	
    str	    r1,[r0]

    ;****************************************
    ;*  change BDMACON reset value for BDMA *   
    ;****************************************
    ldr     r0,=BDIDES0       
    ldr     r1,=0x40000000   					;BDIDESn reset value should be 0x40000000	 
    str     r1,[r0]

    ldr     r0,=BDIDES1      
    ldr     r1,=0x40000000   					;BDIDESn reset value should be 0x40000000	 
    str     r1,[r0]                        		;DMA FOR IDE

    ;****************************************************
    ;*	Set memory control registers					* 	
    ;****************************************************
    ldr	    r0,=SMRDATA
    ldmia   r0,{r1-r13}
    ldr	    r0,=0x01c80000  ;BWSCON Address
    stmia   r0,{r1-r13}
    
   
    ;****************************************************
    ;*	Initialize stacks								* 
    ;****************************************************
    ldr	    sp, =SVCStack	
    bl	    InitStacks

   
    
    bl      bios_main

;****************************************************
;*	The function for initializing stack				*
;****************************************************
InitStacks
	;Don't use DRAM,such as stmfd,ldmfd......
	;SVCstack is initialized before
	;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'

    mrs	    r0,cpsr
    bic	    r0,r0,#MODEMASK
    orr	    r1,r0,#UNDEFMODE|NOINT
    msr	    cpsr_cxsf,r1			;UndefMode
    ldr	    sp,=UndefStack
	
    orr	    r1,r0,#ABORTMODE|NOINT
    msr	    cpsr_cxsf,r1 	    	;AbortMode
    ldr	    sp,=AbortStack

    orr	    r1,r0,#IRQMODE|NOINT
    msr	    cpsr_cxsf,r1 	    	;IRQMode
    ldr	    sp,=IRQStack
	
    orr	    r1,r0,#FIQMODE|NOINT
    msr	    cpsr_cxsf,r1 	    	;FIQMode
    ldr	    sp,=FIQStack

    bic	    r0,r0,#MODEMASK
    orr	    r1,r0,#SVCMODE|NOINT
    msr	    cpsr_cxsf,r1 	    	;SVCMode
    ldr	    sp,=SVCStack

									;USER mode is not initialized.
    mov	    pc,lr 					;The LR register may be not valid for the mode changes.
    
;****************************************************
;*	The function for entering power down mode		*
;****************************************************
;void EnterPWDN(int CLKCON);

EnterPWDN
    mov	    r2,r0               ;r0=CLKCON
    ldr	    r0,=REFRESH		
    ldr	    r3,[r0]
    mov	    r1, r3
    orr	    r1, r1, #0x400000   ;self-refresh enable
    str	    r1, [r0]

    nop     ;Wait until self-refresh is issued. May not be needed.
    nop     ;If the other bus master holds the bus, ...
    nop	    ;mov r0, r0
    nop
    nop
    nop
    nop

;enter POWERDN mode
    ldr	    r0,=CLKCON
    str	    r2,[r0]

;wait until enter SL_IDLE,STOP mode and until wake-up
    ldr	    r0,=0x10
0   subs    r0,r0,#1
    bne	    %B0

;exit from DRAM/SDRAM self refresh mode.
    ldr	    r0,=REFRESH
    str	    r3,[r0]
    mov	    pc,lr

   
    

;*****************************************************************
;* Memory configuration has to be optimized for best performance *
;* The following parameter is not optimized.                     *
;*****************************************************************

;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz. 

;bank0	16bit BOOT ROM
;bank1	8bit NandFlash
;bank2	16bit IDE
;bank3	8bit UDB
;bank4	rtl8019
;bank5	ext
;bank6	16bit SDRAM
;bank7	16bit SDRAM

	LTORG

SMRDATA DATA

    DCD 0x11111110			;Bank0=16bit BootRom(SST39vf160) all 16bit
   	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))	;GCS0
	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))	;GCS1 
	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))	;GCS2
	DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))	;GCS3
	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))	;GCS4
	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))	;GCS5
	DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))														;GCS6
	DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))														;GCS7
	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)	;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
	DCD 0x10				;SCLK power down mode, BANKSIZE 32M/32M
	DCD 0x20				;MRSR6 CL=2clk
	DCD 0x20				;MRSR7
   
	
	ALIGN

	AREA RamData, DATA, READWRITE
	
	MAP (_VIDEO_ADDRESS)
	
Videodata   FIELD 	256*512
 
	MAP	(_ISR_STARTADDRESS-256*5-256)
				
UserStack	FIELD	256		;10001a00
SVCStack	FIELD	256		;10001b00
UndefStack	FIELD	256		;10001c00
AbortStack	FIELD	256		;10001d00
IRQStack	FIELD	256		;10001e00
FIQStack	FIELD	0		;10001e00



		END