/* $Id: //depot/software/SDK/Triscend/a7hal/include/triscend_a7s.h#4 $ *//* *************************************************************************** *  triscend_a7.h * *  Copyright (c) 2000, 2001 Triscend Corporation. All rights reserved. * *************************************************************************** */#ifndef _TRISCEND_A7_H#define _TRISCEND_A7_H/* ********************************************************** *  Memory Map ********************************************************** */#define EXTERNAL_SDRAM_BASE  0xc0000000#define EXTERNAL_SDRAM_SIZE  0x10000000#define EXTERNAL_FLASH_BASE  0xd0000000#define EXTERNAL_FLASH_SIZE  0x01000000#define CONTROL_REG_BASE     0xd1010000#define CONTROL_REG_SIZE     0x00010000#define TEST_AREA_BASE       0xd1020000#define TEST_AREA_SIZE       0x00010000#define INTERNAL_RAM_BASE    0xd1030000#define INTERNAL_RAM_SIZE    0x00004000#define CONFIG_MEM_BASE      0xd1040000#define CONFIG_MEM_SIZE      0x00040000/* ********************************************************** *  Field and Bit Manipulation Defines and Macros ********************************************************** */#define A7_REG(reg) (*(volatile unsigned int*)(reg))#define BIT_MASK(bitIdx) (1 << (bitIdx))#define FIELD_MASK(fieldIdx,nBits) (((1 << (nBits)) - 1) << (fieldIdx))#define GET_BIT(addr32,bitIdx) (*(volatile unsigned int*)(addr32) & (1 << (bitIdx)) ? 1 : 0)#define PUT_BIT(addr32,bitIdx,bitVal) (*(volatile unsigned int*)(addr32) = (0 == (bitVal)) ? *(volatile unsigned int*)(addr32) & ~(1 << (bitIdx)) : *(volatile unsigned int*)(addr32) | (1 << (bitIdx)))#define SET_BIT(addr32,bitIdx) (*(volatile unsigned int*)(addr32) |= (1 << (bitIdx)))#define CLR_BIT(addr32,bitIdx) (*(volatile unsigned int*)(addr32) &= ~(1 << (bitIdx)))#define GET_FIELD(addr32,fieldIdx,nBits) ((*(volatile unsigned int*)(addr32) >> (fieldIdx)) & ((1 << (nBits)) - 1))#define PUT_FIELD(addr32,fieldIdx,nBits,fieldValue) (*(volatile unsigned int*)(addr32) = (*(volatile unsigned int*)(addr32) & ~FIELD_MASK(fieldIdx,nBits)) | (((fieldValue) << (fieldIdx)) & FIELD_MASK(fieldIdx,nBits)))#define SET_FIELD(addr32,fieldIdx,nBits) (*(volatile unsigned int*)(addr32) |= FIELD_MASK(fieldIdx,nBits))#define CLR_FIELD(addr32,fieldIdx,nBits) (*(volatile unsigned int*)(addr32) &= ~FIELD_MASK(fieldIdx,nBits))/* ********************************************************** *  Control Register Base Address Definitions ********************************************************** */#define MSS_BASE    0xd1010000#define SYS_BASE    0xd1010100#define INT_BASE    0xd1010200#define REMAP_BASE  0xd1010400#define TIMER_BASE  0xd1010500#define WD_BASE     0xd1010600#define CFG_BASE    0xd1010700#define DMA_BASE    0xd1010800#define UART_BASE   0xd1010900#define BPU_BASE    0xd1010a00#define PU_BASE     0xd1011100/* ********************************************************** * Memory Subsystem Unit Definition ********************************************************** *//* *  Memory Subsystem Configuration Register (read/write) */#define MSS_CONFIG_REG          (MSS_BASE + 0x00)#define MSS_CONFIG_RESET_VALUE  0x00004002#define BUS_MODE_FIELD             0#define   NBITS_BUS_MODE             4#define MIU_DEV_WIDTH_FIELD        4#define   NBITS_MIU_DEV_WIDTH        2#define SDIU_DEV_WIDTH_FIELD       6#define   NBITS_SDIU_DEV_WIDTH       2#define R_MAP_FIELD                8#define   NBITS_R_MAP                2#define B_MAP_FIELD               10#define   NBITS_B_MAP                3#define N_BANK_BIT                13#define NE_BANK_BIT               14#define PIPE_BIT                  15#define SDRAM_DMA_BUF_EN_FIELD    16#define   NBITS_SDRAM_DMA_BUF_EN     4#define FLASH_DMA_BUF_EN_FIELD    20#define   NBITS_FLASH_DMA_BUF_EN     4#define MSS_FLASH_X16             24/* The following fields are now deleted#define MSS_ARB_FIELD             24#define   NBITS_MSS_ARB              2*//* *  Static Memory Interface Timing Control Register (read/write) */#define MSS_TIM_CTRL_REG          (MSS_BASE + 0x04)#define MSS_TIM_CTRL_RESET_VALUE  0x00077777#define WC_SETUP_FIELD      0#define   NBITS_WC_SETUP      4#define WC_WIDTH_FIELD      4#define   NBITS_WC_WIDTH      4#define WC_HOLD_FIELD       8#define   NBITS_WC_HOLD       4#define RC_SETUP_FIELD     12#define   NBITS_RC_SETUP      4#define RC_WIDTH_FIELD     16#define   NBITS_RC_WIDTH      4/* *  SDRAM Mode Register (read/write) */#define MSS_SDR_MODE_REG          (MSS_BASE + 0x08)#define MSS_SDR_MODE_RESET_VALUE  0x02223222#define TRP_FIELD          0#define   NBITS_TRP          3#define TRCD_FIELD         4#define   NBITS_TRCD         3#define TWR_FIELD          8#define   NBITS_TWR          3#define TRC_FIELD         12#define   NBITS_TRC          3#define MODE_REG_FIELD    16#define   NBITS_MODE_REG    14/* *  SDRAM Control Register (read/write) */#define MSS_SDR_CTRL_REG          (MSS_BASE + 0x0c)#define MSS_SDR_CTRL_RESET_VALUE  0x00000000#define PWR_MAN_FIELD         0#define   NBITS_PWR_MAN         3#define RFSH_RATE_FIELD      16#define   NBITS_RFSH_RATE      12#define RFSH_BURST_FIELD     28#define   NBITS_RFSH_BURST      4/* *  SDRAM Status Register (read only) */#define MSS_STATUS_REG          (MSS_BASE + 0x10)#define MSS_STATUS_RESET_VALUE  0x00000001#define SD_STATUS_FIELD    0#define   NBITS_SD_STATUS    3#define RFSH_OVF_BIT       3/* *  SDRAM Status Clear Register (write only) *      write 1 to clear the corresponding status reg bit */#define MSS_STATUS_CLEAR_REG  (MSS_BASE + 0x14)#define RFSH_OVF_CLR_BIT   3/* ********************************************************** *  System Control Registers ********************************************************** *//* *  Clock Control Register (read/write) *      Use this register to select which portion of the *      device is turned off or kept on in power down mode. *      For any of the bits set, the corresponding circuit *      is be turned off in power down. *      A "0" will keep the circuit running at all times. *      The PLL output frequency = PLL_DIV x 32KHz *      PLL_SCALE:   PLL Pre-scale Value: *       0             1 *       1             2 *       2             4 *       4             8 *       8            16 *      16            32 */#define SYS_CLOCK_CONTROL_REG      (SYS_BASE + 0x00)#define CLOCK_CONTROL_RESET_VALUE  0x00040000#define CLK_SEL_BIT        0#define PLL_SEL_BIT        1#define CSL_SEL_BIT        2#define CK_EN_BIT          3#define XTAL_EN_BIT        4#define PLL_EN_BIT         5#define PLL_TEST_BIT       6#define REF_SEL_BIT        7#define PLL_DIV_FIELD      8#define   NBITS_PLL_DIV    12#define PLL_SCALE_FIELD    24#define   NBITS_PLL_SCALE     5/* *  PLL Status Register (read only) */#define SYS_PLL_STATUS_REG      (SYS_BASE + 0x04)#define PLL_STATUS_RESET_VALUE  0x00000001#define PLL_NOT_LOCK_BIT   0#define PLL_LOCK_BIT       1/* *  PLL Status Clear Register (write only) */#define SYS_PLL_STATUS_CLEAR_REG  (SYS_BASE + 0x08)#define PLL_NOT_LOCK_CLEAR_BIT   0#define PLL_LOCK_CLEAR_BIT       1/* *  Reset Control Register (read/write) *      The SYS_RESET bit is used by software to reset the *      system as seen by the user. It resets the CPU, the *      bus and all the peripherals without affecting the *      configuration of the device. *      The bit is self-clearing. */#define SYS_RESET_CONTROL_REG      (SYS_BASE + 0x0c)#define RESET_CONTROL_RESET_VALUE  0x00000000#define SLAVE_DIS_BIT    1#define SYS_RESET_BIT    2/* *  Power Down Control Register (read/write) *      User can select which portion of the device is *      turned off or kept on during power down mode. *      Setting a bit turns off the circuit in power down. *      A zero keeps the circuit running at all times. */#define SYS_POWER_CONTROL_REG      (SYS_BASE + 0x10)#define POWER_CONTROL_RESET_VALUE  0x00000000#define PD_BCK_EN_BIT      0#define PD_CSL_BCK_EN_BIT  1#define PD_OSC_EN_BIT      2#define PD_IO_EN_BIT       3#define PD_BIT             4#define POR_DIS_BIT        5/* *  Pause Register (write only) *      Writing to this register puts the ARM core (only) in *      a low power state until receiving an interrupt. */#define REMAP_PAUSE_REG  (REMAP_BASE + 0x00)/* *  Identification Register (read only) */#define REMAP_IDENTIFICATION_REG  (REMAP_BASE + 0x10)#define TRISCEND_TA7S20  0x1803d2ff/* *  Revision Register (read only) *      Revision = 0 for first device */#define REMAP_REVISION_REG  (REMAP_BASE + 0x14)#define TRISCEND_TA7S20_REV113  0x00000113/* ****************** OBSOLETE *******************/#define TRISCEND_TA7S20_REV111  0x00000111#define TRISCEND_TA7S20_REV000  0x00000000/************************************************//* *  Clear Reset Map Register (write only) *      Writing to this address causes a system memory map switch from the *      user initial memory map to the one used during normal operation. *      It effectively clears the Flash alias bit in the Alias Enable Register. */#define REMAP_CLEAR_RESET_MAP_REG  (REMAP_BASE + 0x20)/* *  Reset Status Register (read only) *      Indicates the cause of the latest reset. *      Default reset value depends on reset cause. */#define REMAP_RESET_STATUS_REG  (REMAP_BASE + 0x30)#define POR_BIT         0#define CFG_RST_BIT     1#define RST_PIN_BIT     2#define J_CFG_RST_BIT   3#define CPU_RST_BIT     4#define J_CPU_RST_BIT   5#define WD_RST_BIT      6#define APP_RST_BIT     7#define SYS_RST_BIT     8#define J_SYS_RST_BIT   9#define SOFT_RST_BIT   10/* *  Reset Status Clear Register (write only) *      Writing a "1" clears the corresponding bit in Reset Status Register. *      Writing a "0" has no effect. */#define REMAP_RESET_STATUS_CLEAR_REG  (REMAP_BASE + 0x34)#define POR_CLR_BIT         0#define CFG_RST_CLR_BIT     1#define RST_PIN_CLR_BIT     2#define J_CFG_RST_CLR_BIT   3#define CPU_RST_CLR_BIT     4#define J_CPU_RST_CLR_BIT   5#define WD_RST_CLR_BIT      6#define APP_RST_CLR_BIT     7#define SYS_RST_CLR_BIT     8#define J_SYS_RST_CLR_BIT   9#define SOFT_RST_CLR_BIT   10/* *  Pin Status Register (read only) *      This register enables software to get the status of *      some static pins of the device. */#define REMAP_PIN_STATUS_REG  (REMAP_BASE + 0x38)#define VSYS_BIT       0#define RSTN_BIT       1#define SLAVEN_BIT     2#define VSYS_GOOD_BIT  3#define VSYS_BAD_BIT   4/* *  Pin Status Clear Register (write only) *      Writing a "1" clears the corresponding bit in the Pin Status Register. *      Writing a "0" has no effect. */#define REMAP_PIN_STATUS_CLEAR_REG  (REMAP_BASE + 0x3c)#define VSYS_GOOD_CLR_BIT  3#define VSYS_BAD_CLR_BIT   4/* *  Alias Enable Register (read/write) *      This register defines which alias is enabled at the bottom of the *      memory starting at address 0. If more than one alias is enabled, *      they are overlaid over each other with the following priority *      (from highest to lowest priority): ROM, FLASH, SRAM, SDRAM. */#define REMAP_ALIAS_ENABLE_REG    (REMAP_BASE + 0x40)#define ALIAS_ENABLE_RESET_VALUE  0x0000000f#define ROM_AEN_BIT     0#define FLASH_AEN_BIT   1#define SRAM_AEN_BIT    2#define SDRAM_AEN_BIT   3/* *  SRAM Config Register (read/write) */#define REMAP_SRAM_CONFIG_REG    (REMAP_BASE + 0x44)#define SRAM_CONFIG_RESET_VALUE  0x00000000#define SRAM_PRIO_BIT             0#define SRAM_SIZE_BIT             1#define SRAM_PROTECT_FIELD        2#define   NBITS_SRAM_PROTECT        4/* *  SRAM Base Address Register (read/write) *      The internal SRAM can be relocated using this register */#define REMAP_SRAM_BASE_ADR_REG    (REMAP_BASE + 0x48)#define SRAM_BASE_ADR_RESET_VALUE  0x0d1030000#define SRAM_BASE_ADR_FIELD   14#define   NBITS_SRAM_BASE_ADR    18/* *  Access Protect Register (read/write) *      When the dmaDis bit is set, DMA writes are not *      allowed into the control register area. */#define REMAP_ACC_PROTECT_REG    (REMAP_BASE + 0x4c)#define ACC_PROTECT_RESET_VALUE  0x00000001#define DMA_DIS_BIT  0#define TEST_EN_BIT  1/* ********************************************************** *  Configuration Unit Definition ********************************************************** *//* *  Configuration Control Register (read/write) */#define CFG_CONFIG_CONTROL_REG      (CFG_BASE + 0x00)#define CONFIG_CONTROL_RESET_VALUE  0x00000000#define EN_ZIP_BIT       0#define EN_REG_BIT       1#define EN_IO_BIT        2#define CONFIG_DONE_BIT  4#define DEC_EN_BIT       5#define CFGENS_EN_BIT    6#define CFG_STOP_BIT     7/* *  Configuration Timing Register (read/write) *      CSL Configuration Access Wait States: *          generated by config unit in response to CSL reads. *          number of wait states = cslWait *      PIO Phase Delay: *          length in clock cycles of PIO config read & write phases. *          length in clock cycles = (pioPhase - 1)