*/#define CFG_CONFIG_TIMING_REG      (CFG_BASE + 0x04)#define CONFIG_TIMING_RESET_VALUE  0x00000024#define CSL_WAIT_FIELD       0#define   NBITS_CSL_WAIT       3#define PIO_PHASE_FIELD      3#define   NBITS_PIO_PHASE      3/* *  IO Recover Register (read/write) */#define CFG_IO_RECOVER_REG      (CFG_BASE + 0x08)#define IO_RECOVER_RESET_VALUE  0x00008061#define SD_SEL_BIT           0#define CEN1_SEL_BIT         1#define CEN2_SEL_BIT         2#define CEN3_SEL_BIT         3#define XDONE_SEL_BIT        4#define A18_SEL_BIT          5#define A19_SEL_BIT          6#define A20_SEL_BIT          7#define A21_SEL_BIT          8#define A22_SEL_BIT          9#define A23_SEL_BIT         10#define A24_TO_A31_SEL_BIT  11#define D8_TO_D15_SEL_BIT   12#define D16_TO_D31_SEL_BIT  13#define ECLK_SEL_BIT        14#define SDCEN1_SEL_BIT      15/* *  Configuration Protection Register (read/write) *      When a protection bit is set, the configuration plane *      is protected from read or write accesses. (Read data = 0). *      Once this bit is set, it can only be cleared through a power cycle. */#define CFG_CONFIG_PROTECT_REG      (CFG_BASE + 0x0c)#define CONFIG_PROTECT_RESET_VALUE  0x00000000#define RD_SECURE_BIT   0#define WR_SECURE_BIT   1/* ********************************************************** * Interrupt Unit Definition ********************************************************** *//* *  Interrupt Registers Definition */#define INT_IRQ_STATUS_REG          (INT_BASE + 0x00)   // read only#define INT_IRQ_RAW_STATUS_REG      (INT_BASE + 0x04)   // read only#define INT_IRQ_ENABLE_REG          (INT_BASE + 0x08)   // read/write#define INT_IRQ_ENABLE_CLEAR_REG    (INT_BASE + 0x0c)   // write only#define INT_IRQ_SOFT_REG            (INT_BASE + 0x10)   // write only#define INT_FIQ_STATUS_REG          (INT_BASE + 0x100)  // read only#define INT_FIQ_RAW_STATUS_REG      (INT_BASE + 0x104)  // read only#define INT_FIQ_ENABLE_REG          (INT_BASE + 0x108)  // read/write#define INT_FIQ_ENABLE_CLEAR_REG    (INT_BASE + 0x10c)  // write only#define INT_IRQ_STEER_REG           (INT_BASE + 0x110)  // write only#define IRQ_STATUS_RESET_VALUE      0x00000000#define IRQ_RAW_STATUS_RESET_VALUE  0x00000000#define IRQ_ENABLE_RESET_VALUE      0x00000000#define FIQ_STATUS_RESET_VALUE      0x00000000#define FIQ_RAW_STATUS_RESET_VALUE  0x00000000#define FIQ_ENABLE_RESET_VALUE      0x00000000#define FIQ_BIT              0#define IRQ_SOFTWARE_BIT     1#define IRQ_SERIAL_0_BIT     2#define IRQ_TIMER_0_BIT      3#define IRQ_TIMER_1_BIT      4#define IRQ_SERIAL_1_BIT     5#define IRQ_WATCHDOG_BIT     6#define IRQ_DMA_0_BIT        7#define IRQ_DMA_1_BIT        8#define IRQ_DMA_2_BIT        9#define IRQ_DMA_3_BIT       10#define IRQ_CSL_USER_0_BIT  11#define IRQ_CSL_USER_1_BIT  12#define IRQ_CSL_USER_2_BIT  13#define IRQ_JTAG_BIT        14#define IRQ_BREAKPOINT_BIT  15/* *********************************************************** * DMA Unit Definition *********************************************************** *//* *  DMA Control Registers Definition (read/write) */#define DMA0_CONTROL_REG         (DMA_BASE + 0x00)#define DMA1_CONTROL_REG         (DMA_BASE + 0x40)#define DMA2_CONTROL_REG         (DMA_BASE + 0x80)#define DMA3_CONTROL_REG         (DMA_BASE + 0xc0)#define DMA_CONTROL_RESET_VALUE  0x00000000#define CLEAR_BIT                      0#define DMA_ENABLE_BIT                 1#define DMA_INIT_BIT                   2#define CONT_BIT                       3#define SFT_REQ_BIT                    4#define BLOCK_EN_BIT                   5#define TRANS_DIR_FIELD                6#define   NBITS_TRANS_DIR                2#define SRC_ADDR_MODE_FIELD            8#define   NBITS_SRC_ADDR_MODE            2#define DEST_ADDR_MODE_FIELD          10#define   NBITS_DEST_ADDR_MODE           2#define TRANS_SIZE_FIELD              12#define   NBITS_TRANS_SIZE               2#define METHOD_BIT                    14#define AUX_DIS_BIT                   15#define CRC_EN_BIT                    16#define BROADCAST_BIT                 17/* *  DMA Interrupt Registers Definitions */#define DMA0_INT_ENABLE_REG         (DMA_BASE + 0x04)   // read/write#define DMA1_INT_ENABLE_REG         (DMA_BASE + 0x44)   // read/write#define DMA2_INT_ENABLE_REG         (DMA_BASE + 0x84)   // read/write#define DMA3_INT_ENABLE_REG         (DMA_BASE + 0xc4)   // read/write#define DMA0_INT_REG                (DMA_BASE + 0x08)   // read only#define DMA1_INT_REG                (DMA_BASE + 0x48)   // read only#define DMA2_INT_REG                (DMA_BASE + 0x88)   // read only#define DMA3_INT_REG                (DMA_BASE + 0xc8)   // read only#define DMA0_INT_CLEAR_REG          (DMA_BASE + 0x0c)   // write only#define DMA1_INT_CLEAR_REG          (DMA_BASE + 0x4c)   // write only#define DMA2_INT_CLEAR_REG          (DMA_BASE + 0x8c)   // write only#define DMA3_INT_CLEAR_REG          (DMA_BASE + 0xcc)   // write only#define DMA_INT_ENABLE_RESET_VALUE  0x00000000#define DMA_INT_RESET_VALUE         0x00000000#define TC_BIT        0#define INIT_BIT      1#define OVF_BIT       2#define FULL_BIT      3#define EMPTY_BIT     4#define LAST_BIT      5#define RETRANS_BIT   6#define DESC_BIT      7#define BAD_RETR_BIT  8/* *  DMA Transfer Count Registers Definition */#define DMA0_TRANS_CNT_REG  (DMA_BASE + 0x1c)   // read/write#define DMA1_TRANS_CNT_REG  (DMA_BASE + 0x5c)   // read/write#define DMA2_TRANS_CNT_REG  (DMA_BASE + 0x9c)   // read/write#define DMA3_TRANS_CNT_REG  (DMA_BASE + 0xdc)   // read/write#define TRANS_CNT_FIELD    0#define   NBITS_TRANS_CNT    16#define DMA0_CUR_TRANS_CNT_REG  (DMA_BASE + 0x2c)       // read only#define DMA1_CUR_TRANS_CNT_REG  (DMA_BASE + 0x6c)       // read only#define DMA2_CUR_TRANS_CNT_REG  (DMA_BASE + 0xac)       // read only#define DMA3_CUR_TRANS_CNT_REG  (DMA_BASE + 0xec)       // read only#define CUR_TRANS_CNT_FIELD   TRANS_CNT_FIELD#define   NBITS_CUR_TRANS_CNT   NBITS_TRANS_CNT/* *  DMA Pending Request Counter Register Definition (read only) */#define DMA0_PEND_REQ_REG  (DMA_BASE + 0x30)#define DMA1_PEND_REQ_REG  (DMA_BASE + 0x70)#define DMA2_PEND_REQ_REG  (DMA_BASE + 0xb0)#define DMA3_PEND_REQ_REG  (DMA_BASE + 0xf0)#define PEND_REQ_CTRL_FIELD      0#define   NBITS_PEND_REQ_CTRL     10#define LAST_POST_FIELD         16#define   NBITS_LAST_POST         10/* *  DMA Descriptor Table */#define DMA0_DES_TABLE_ADDR_REG  (DMA_BASE + 0x10)      // read/write#define DMA1_DES_TABLE_ADDR_REG  (DMA_BASE + 0x50)      // read/write#define DMA2_DES_TABLE_ADDR_REG  (DMA_BASE + 0x90)      // read/write#define DMA3_DES_TABLE_ADDR_REG  (DMA_BASE + 0xd0)      // read/write#define DMA0_CUR_DESC_ADDR_REG   (DMA_BASE + 0x20)      // read only#define DMA1_CUR_DESC_ADDR_REG   (DMA_BASE + 0x60)      // read only#define DMA2_CUR_DESC_ADDR_REG   (DMA_BASE + 0xa0)      // read only#define DMA3_CUR_DESC_ADDR_REG   (DMA_BASE + 0xe0)      // read only#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)typedef struct{    unsigned int sourceAddress;    unsigned int reserved;    unsigned int destinationAddress;    unsigned int controlStatus;}DMA_DESCRIPTOR;#endif/* * DMA_DESCRIPTOR controlStatus Definition */#define ACT_WHEN_COMPL_FIELD          0#define   NBITS_ACT_WHEN_COMPL          2#define DESC_INT_BIT                  2#define CRC_CLR_DIS_BIT               3#define CONT_DESC_BIT                 4#define BUFF_STAT_BIT                 5#define TRANS_LENGTH_FIELD           16#define   NBITS_TRANS_LENGTH           16/* *  Other DMA Registers Definition - 32-bit registers */#define DMA0_SRC_ADDR_REG       (DMA_BASE + 0x14)       // read/write#define DMA1_SRC_ADDR_REG       (DMA_BASE + 0x54)       // read/write#define DMA2_SRC_ADDR_REG       (DMA_BASE + 0x94)       // read/write#define DMA3_SRC_ADDR_REG       (DMA_BASE + 0xd4)       // read/write#define DMA0_CUR_SRC_ADDR_REG   (DMA_BASE + 0x24)       // read only#define DMA1_CUR_SRC_ADDR_REG   (DMA_BASE + 0x64)       // read only#define DMA2_CUR_SRC_ADDR_REG   (DMA_BASE + 0xa4)       // read only#define DMA3_CUR_SRC_ADDR_REG   (DMA_BASE + 0xe4)       // read only#define DMA0_DST_ADDR_REG       (DMA_BASE + 0x18)       // read/write#define DMA1_DST_ADDR_REG       (DMA_BASE + 0x58)       // read/write#define DMA2_DST_ADDR_REG       (DMA_BASE + 0x98)       // read/write#define DMA3_DST_ADDR_REG       (DMA_BASE + 0xd8)       // read/write#define DMA0_CUR_DEST_ADDR_REG  (DMA_BASE + 0x28)       // read only#define DMA1_CUR_DEST_ADDR_REG  (DMA_BASE + 0x68)       // read only#define DMA2_CUR_DEST_ADDR_REG  (DMA_BASE + 0xa8)       // read only#define DMA3_CUR_DEST_ADDR_REG  (DMA_BASE + 0xe8)       // read only#define DMA_CRC_REG  (DMA_BASE + 0xfc)  // read only/* ********************************************************** * UART Definition ********************************************************** *//* *  Uart Control Register Structure (read/write) */#define UART0_CONTROL_REG         (UART_BASE + 0x00)#define UART1_CONTROL_REG         (UART_BASE + 0x40)#define UART_CONTROL_RESET_VALUE  0x00000000#define UART_PRESCALE_FIELD     0#define   NBITS_UART_PRESCALE     8#define PRESCALE_EN_BIT         8#define MODEM_EN_BIT            9#define TX_DMA_EN_BIT          16#define TX_DMA_SEL_FIELD       17#define   NBITS_TX_DMA_SEL        2/* * reserved bit 19 */#define RX_DMA_EN_BIT          20#define RX_DMA_SEL_FIELD       21#define   NBITS_RX_DMA_SEL        2/* *  DLAB=0: Uart Rx Tx Register Structure       (read/write) *  DLAB=1: Uart Divisor LSB Register Structure (read/write) */#define UART0_RX_TX_REG  (UART_BASE + 0x20)#define UART1_RX_TX_REG  (UART_BASE + 0x60)#define DATA_FIELD    0#define   NBITS_DATA    8#define UART0_DIVISOR_LSB_REG  (UART_BASE + 0x20)#define UART1_DIVISOR_LSB_REG  (UART_BASE + 0x60)#define DIVISOR_LSB_FIELD    0#define   NBITS_DIVISOR_LSB    8/* *  DLAB=0: Uart Interrupt Enable Register Structure (read/write) *  DLAB=1: Uart Divisor MSB Register Structure      (read/write) */#define UART0_INT_ENABLE_REG         (UART_BASE + 0x24)#define UART1_INT_ENABLE_REG         (UART_BASE + 0x64)#define UART_INT_ENABLE_RESET_VALUE  0x00000000#define RDRE_BIT   0#define THREE_BIT  1#define RLSE_BIT   2#define MSE_BIT    3#define UART0_DIVISOR_MSB_REG  (UART_BASE + 0x24)#define UART1_DIVISOR_MSB_REG  (UART_BASE + 0x64)#define DIVISOR_MSB_FIELD     0#define   NBITS_DIVISOR_MSB     8/* *  Uart Interrupt ID Register Structure (read only) *  Uart Fifo Control Register Structure (write only) */#define UART0_INT_ID_REG         (UART_BASE + 0x28)#define UART1_INT_ID_REG         (UART_BASE + 0x68)#define UART_INT_ID_RESET_VALUE  0x00000001#define INT_ID_FIELD            0#define   NBITS_INT_ID            4#define FIFO_MODE_FIELD         6#define   NBITS_FIFO_MODE         2#define UART0_FIFO_CTRL_REG         (UART_BASE + 0x28)#define UART1_FIFO_CTRL_REG         (UART_BASE + 0x68)#define UART_FIFO_CTRL_RESET_VALUE  0x00000000#define FIFO_MODE_ENABLE_BIT      0#define RX_FIFO_CLR_BIT           1#define TX_FIFO_CLR_BIT           2#define FIFO_TRIG_LEVEL_FIELD     6#define   NBITS_FIFO_TRIG_LEVEL     2/* *  Uart Line Control Register Structure (read/write) */#define UART0_LINE_CONTROL_REG         (UART_BASE + 0x2c)#define UART1_LINE_CONTROL_REG         (UART_BASE + 0x6c)#define UART_LINE_CONTROL_RESET_VALUE  0x00000000#define STB_WLS_FIELD     0#define   NBITS_STB_WLS     3#define PEN_BIT           3#define EPS_BIT           4#define STICK_PARITY_BIT  5#define BREAK_BIT         6#define DLAB_BIT          7/* *  Uart Modem Control Register Structure (read/write) */#define UART0_MODEM_CONTROL_REG         (UART_BASE + 0x30)#define UART1_MODEM_CONTROL_REG         (UART_BASE + 0x70)#define UART_MODEM_CONTROL_RESET_VALUE  0x00000000#define DTR_BIT   0#define RTS_BIT   1#define LOOP_BIT  3/* *  Uart Line Status Register Structure (read only) */#define UART0_LINE_STATUS_REG         (UART_BASE + 0x34)#define UART1_LINE_STATUS_REG         (UART_BASE + 0x74)#define UART_LINE_STATUS_RESET_VALUE  0x00000060#define DR_BIT     0#define OE_BIT     1#define PE_BIT     2#define FE_BIT     3#define BI_BIT     4#define THRE_BIT   5#define TEMT_BIT   6#define ERROR_BIT  7/* *  Uart Modem Status Register Structure (read only) */#define UART0_MODEM_STATUS_REG         (UART_BASE + 0x38)#define UART1_MODEM_STATUS_REG         (UART_BASE + 0x78)#define UART_MODEM_STATUS_RESET_VALUE  0x00000000#define DELTA_CTS_BIT   0#define DELTA_DSR_BIT   1#define TERI_BIT        2#define DELTA_DCD_BIT   3#define CTS_BIT         4#define DSR_BIT         5#define RI_BIT          6#define DCD_BIT         7/* *  Uart Scratchpad Register Structure (read/write) */#define UART0_SCRATCHPAD_REG  (UART_BASE + 0x3c)#define UART1_SCRATCHPAD_REG  (UART_BASE + 0x7c)/* ********************************************************** * Timer Unit Definition ********************************************************** *//* *  Timer Load Register Structure (read/write) */#define TIMER0_LOAD_REG  (TIMER_BASE + 0x00)#define TIMER1_LOAD_REG  (TIMER_BASE + 0x20)#define LOAD_FIELD       0#define   NBITS_LOAD      16/* *  Timer Value Register Structure (read only) */#define TIMER0_VALUE_REG  (TIMER_BASE + 0x04)#define TIMER1_VALUE_REG  (TIMER_BASE + 0x24)#define VALUE_FIELD      0#define   NBITS_VALUE     16/* *  Timer Control Register Structure (read/write) */#define TIMER0_CONTROL_REG         (TIMER_BASE + 0x08)#define TIMER1_CONTROL_REG         (TIMER_BASE + 0x28)#define TIMER_CONTROL_RESET_VALUE  0x00000000#define PRESCALE_FIELD       2#define   NBITS_PRESCALE       2#define TIM_MODE_BIT         6#define TIM_ENABLE_BIT       7/* *  Timer Clear Register Structure (write only) *      Write a "1" to clear the timer interrupt. *      Writing a "0" has no effect. */#define TIMER0_CLEAR_REG  (TIMER_BASE + 0x0c)#define TIMER1_CLEAR_REG  (TIMER_BASE + 0x2c)#define TIM_INT_CLEAR_BIT   0/* **********************************************************