* Watchdog Unit Definition ********************************************************** *//* *  Watchdog Control Register Structure (read/write) *      Writing a '1' to the WD_RESET bit will reset the watchdog timer, *      including its interrupt and reset logic. This bit is self-clearing. */#define WATCHDOG_CONTROL_REG          (WD_BASE + 0x00)#define WATCHDOG_CONTROL_RESET_VALUE  0x00000000#define WD_ENABLE_BIT    0#define WD_RESET_BIT     1#define EN_WD_RST_BIT    2/* *  Watchdog Timeout Value Register Structure (read/write) */#define WATCHDOG_TIMEOUT_VAL_REG  (WD_BASE + 0x04)/* *  Watchdog Current Value Register Structure (read only) */#define WATCHDOG_CURRENT_VAL_REG  (WD_BASE + 0x08)/* *  Watchdog Clear Register Structure (write only) *      Writing a '1' to the WD_INT_CLR bit will clear the watchdog interrupt. *      Writing a "0" has no effect. */#define WATCHDOG_CLEAR_REG  (WD_BASE + 0x0c)#define WD_INT_CLR_BIT   0/* ****************************************************************************** * Breakpoint Unit Definition ****************************************************************************** *//* * Breakpoint Control Register definition (read/write) */#define BPU_BRK_CONTROL_REG      (BPU_BASE + 0x00)#define BRK_CONTROL_RESET_VALUE  0x00000000#define CPU_STIM_FIELD                 0#define   NBITS_CPU_STIM                 3#define CSL_FREEZE_BIT                 3#define CSL_MATCH_BIT                  4#define BP_TYPE_FIELD                  5#define   NBITS_BP_TYPE                  3#define RESTART_BIT                    8#define BP_ENABLE_FIELD                9#define   NBITS_BP_ENABLE                2#define BP0_NOT_MATCH_BIT             13#define BP1_NOT_MATCH_BIT             14#define ARB_FREEZE_BIT                15#define BUS_SEL_BIT                   16#define BP0_DATA_SEL_BIT              17#define BP1_DATA_SEL_BIT              18#define TRACE_EN_BIT                  20#define TRACE_FORMAT_FIELD            21#define   NBITS_TRACE_FORMAT             3#define CSL_CAPT_EN_BIT               24#define BCLK_FREEZE_BIT               25#define CPU_DBG_EN_BIT                26/* * Breakpoint Bus Mask0/Compare0 Registers Definition (read/write) */#define BPU_BRK0_BUS_MASK0_REG  (BPU_BASE + 0x04)#define BPU_BRK0_BUS_COMP0_REG  (BPU_BASE + 0x24)#define BPU_BRK1_BUS_MASK0_REG  (BPU_BASE + 0x14)#define BPU_BRK1_BUS_COMP0_REG  (BPU_BASE + 0x34)/* * Breakpoint Bus Mask1/Compare1 Registers Definition (read/write) */#define BPU_BRK0_BUS_MASK1_REG  (BPU_BASE + 0x08)#define BPU_BRK0_BUS_COMP1_REG  (BPU_BASE + 0x28)#define BPU_BRK1_BUS_MASK1_REG  (BPU_BASE + 0x18)#define BPU_BRK1_BUS_COMP1_REG  (BPU_BASE + 0x38)/* * Breakpoint Bus Mask2/Compare2 Registers Definition (read/write) */#define BPU_BRK0_BUS_MASK2_REG  (BPU_BASE + 0x0c)#define BPU_BRK0_BUS_COMP2_REG  (BPU_BASE + 0x2c)#define BPU_BRK1_BUS_MASK2_REG  (BPU_BASE + 0x1c)#define BPU_BRK1_BUS_COMP2_REG  (BPU_BASE + 0x3c)/* * BUS MASK 2 for CPU BUS */#define NRW_BIT               0#define MAS_FIELD             1#define   NBITS_MAS             2#define LOCK_BIT              3#define SEQ_BIT               4#define ABORT_BIT             5#define NTRANS_BIT            6#define NMREQ_BIT             7#define OPC_BIT               8#define DBGACK_BIT           17/* * BUS MASK2 for CSI BUS */#define SW_DMA_ACK_FIELD      0#define   NBITS_SW_DMA_ACK      4#define SW_MODE_FIELD         4#define   NBITS_SW_MODE         4#define SW_DMA_CTRL_FIELD     8#define   NBITS_SW_DMA_CTRL     4#define SW_SIZE_FIELD        12#define   NBITS_SW_SIZE         2#define SW_RD_EN_BIT         14#define SW_WR_EN_BIT         15#define SW_BP_CTRL_BIT       16#define RD_OR_WR_BIT         18#define OR_DMA_ACK_BIT       19#define RD_WR_ACK_BIT        20/* * Breakpoint Bus Mask3 Registers Definition (read/write) */#define BPU_BRK0_BUS_MASK3_REG  (BPU_BASE + 0x10)#define BPU_BRK1_BUS_MASK3_REG  (BPU_BASE + 0x20)#define FR_FIELD    0#define   NBITS_FR   11/* * Breakpoint Counter Compare/Out Registers Definition */#define BPU_BRK_CNT_COMP_REG  (BPU_BASE + 0x44) // read/write#define BPU_BRK_CNT_OUT_REG   (BPU_BASE + 0x48) // read only#define BRK_CNT0_FIELD     0#define   NBITS_BRK_CNT0    16#define BRK_CNT1_FIELD    16#define   NBITS_BRK_CNT1    16/* * Trace Buffer Address Pointer Register Definition (read only) * Trace Counter Register Definition (read/write) */#define BPU_BRK_TR_ADDR_REG  (BPU_BASE + 0x4c)#define TRACE_ADDR_FIELD      0 // read only#define   NBITS_TRACE_ADDR      9       // read only#define TR_ADDR_FLIP_BIT      9 // read only#define TRACE_CNT_FIELD      16 // read/write#define   NBITS_TRACE_CNT       9       // read/write/* * Breakpoint Interrupt Clear Register Definition (write only) */#define BPU_BRK_INT_CLEAR_REG  (BPU_BASE + 0x50)#define BRK_INT_CLEAR_BIT   0/* * Breakpoint Status Register Definition (read only) */#define BPU_BRK_STATUS_REG  (BPU_BASE + 0x54)#define STAT_CPU_FREEZE_BIT   0#define STAT_CPU_IRQ_BIT      1#define STAT_ARB_FREEZE_BIT   6#define STAT_CSL_MATCH_BIT    7#define STAT_CSL_FREEZE_BIT   8#define STAT_CSL_STEP_BIT     9#define STAT_TRACE_FIN_BIT   10#define STAT_TRACE_EN_BIT    11#define STAT_BP0_CNT_TC_BIT  12#define STAT_BP1_CNT_TC_BIT  13#define STAT_BP_EVENT_BIT    14/* * Trace Buffer Definition *     The Trace Buffer is implemented in the Scratchpad RAM. *     The buffer is a data array of 128-bit wide and 512 deep. *     The trace can be moved relative to a programmed breakpoint event. *//* * CSI Trace Capture Description */#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)typedef struct{    unsigned int CsiSlaveWriteBusAddr;    unsigned int CsiSlaveWriteBusData;    unsigned int CsiControl;    unsigned int CsiMasterReadData;}CSI_TRACE;#endif/* * CsiControl trace definition */#define CSI_SW_DMAACK_FIELD      0#define   NBITS_CSI_SW_DMAACK      4#define CSI_SW_MODE_FIELD        4#define   NBITS_CSI_SW_MODE        4#define CSI_SW_DMA_CTRL_FIELD    8#define   NBITS_CSI_SW_DMA_CTRL    4#define CSI_SW_SIZE_FIELD       12#define   NBITS_CSI_SW_SIZE        2#define CSI_SW_RD_EN_BIT        14#define CSI_SW_WR_EN_BIT        15#define CSI_SR_BP_CTRL_BIT      16#define CSI_RD_OR_WR_BIT        18#define CSI_OR_DMA_ACK_BIT      19#define CSI_FR_FIELD            20#define   NBITS_CSI_FR            11#define CSI_SW_WAIT_NOW_BIT     31/* * CPU Trace Capture Description */#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)typedef struct{    unsigned int CpuAddress;    unsigned int CpuData;    unsigned int CpuControl;    unsigned int Reserved;}CPU_TRACE;#endif/* * CpuControl trace definition */#define ARM_NRW_BIT         0#define ARM_MAS_FIELD       1#define   NBITS_ARM_MAS       2#define ARM_LOCK_BIT        3#define ARM_SEQ_BIT         4#define ARM_ABORT_BIT       5#define ARM_NTRANS_BIT      6#define ARM_NMREQ_BIT       7#define ARM_NOPC_BIT        8#define ARM_DBGACK_BIT     17#define ARM_CACHELINE_BIT  18#define ARM_TBIT       19#define ARM_NEXEC_BIT      20#define ARM_NM_FIELD       22#define   NBITS_ARM_NM        5#define ARM_NWAIT_BIT      27/* ****************************************************************************** * Protection Unit Registers (PU_BASE) ****************************************************************************** *//* * Protection Unit Control Register definition (read/write) */#define PU_CONTROL_REG         (PU_BASE + 0x04)#define PU_CONTROL_RESET_VALUE 0x00000000#define PROT_EN_BIT    0#define CACHE_EN_BIT   2/* * Cacheable Area Register definition (read/write) */#define PU_CACHEABLE_AREA_REG  (PU_BASE + 0x08)#define C_0_BIT  0#define C_1_BIT  1#define C_2_BIT  2#define C_3_BIT  3#define C_4_BIT  4#define C_5_BIT  5#define C_6_BIT  6#define C_7_BIT  7/* * Protection Area Register definition (read/write) */#define PU_PROTECTION_AREA_REG  (PU_BASE + 0x14)#define AP_0_FIELD      0#define   NBITS_AP_0      2#define AP_1_FIELD      2#define   NBITS_AP_1      2#define AP_2_FIELD      4#define   NBITS_AP_2      2#define AP_3_FIELD      6#define   NBITS_AP_3      2#define AP_4_FIELD      8#define   NBITS_AP_4      2#define AP_5_FIELD     10#define   NBITS_AP_5      2#define AP_6_FIELD     12#define   NBITS_AP_6      2#define AP_7_FIELD     14#define   NBITS_AP_7      2/* * Memory Area Definition Registers definition (read/write) *     These regsiters define 8 programmable regions in memory. */#define PU_AREA_DEF0_REG  (PU_BASE + 0x20)#define PU_AREA_DEF1_REG  (PU_BASE + 0x24)#define PU_AREA_DEF2_REG  (PU_BASE + 0x28)#define PU_AREA_DEF3_REG  (PU_BASE + 0x2c)#define PU_AREA_DEF4_REG  (PU_BASE + 0x30)#define PU_AREA_DEF5_REG  (PU_BASE + 0x34)#define PU_AREA_DEF6_REG  (PU_BASE + 0x38)#define PU_AREA_DEF7_REG  (PU_BASE + 0x3c)#define AREA_EN_BIT           0#define AREA_SIZE_FIELD       1#define   NBITS_AREA_SIZE       5#define AREA_BASE_ADR_FIELD  12#define   NBITS_AREA_BASE      20/* * Cache Invalidate Register definition (write only) *     Reserved. */#define PU_CACHE_INVALIDATE_REG  (PU_BASE + 0x1c)/* ********************************************************** * Debug Unit Definition ********************************************************** *//* * Triscend A7 JTAG Instructions */#define JTAG_EXTEST          0x00#define JTAG_SCAN_N          0x02#define JTAG_INTEST          0x0c#define JTAG_IDCODE          0x0e#define JTAG_BYPASS          0x0f#define JTAG_CLAMP           0x05#define JTAG_HIGHZ           0x07#define JTAG_CLAMPZ          0x09#define JTAG_SAMPLE_PRELOAD  0x03#define JTAG_RESTART         0x04#define JTAG_NONE            0xff/* * Triscend A7 JTAG IDs */#define JTAG_TA7S20     0x1843d2ff#define JTAG_TA7S20_AB  0x1f0f0f0f /*  * Triscend A7 JTAG Scan Chains  *     The DEBUG chain is scanned with the msb first.  *     All other chains are scanned with the lsb first.  */#define SCAN_TEST_CHAIN        0#define DEBUG_CHAIN            1#define ICEBREAKER_CHAIN       2#define BOUNDARY_SCAN_CHAIN    3        // for Triscend internal use only#define INTERNAL_SCAN_CHAIN    5        // for Triscend internal use only#define BUSTAT_CHAIN           6#define BUSCON_CHAIN           7#define MEMORY_RW_CHAIN        9#define MEMORY_RW_INCR_CHAIN  10#define MEMORY_FILL_CHAIN     11#define CRC_CHANNEL_CHAIN     12/* * Bitlengths of Triscend A7 JTAG registers/chains */#define BITLEN_SCAN_N_REG             4#define BITLEN_IDENTIFICATION_REG    32#define BITLEN_BYPASS_REG             1#define BITLEN_INSTRUCTION_REG        4#define BITLEN_DEBUG_CHAIN           33#define BITLEN_ICEBREAKER_CHAIN      38#define BITLEN_BUSTAT_CHAIN          20#define BITLEN_BUSCON_CHAIN          12#define BITLEN_MEMORY_RW_CHAIN       68#define BITLEN_MEMORY_RW_INCR_CHAIN  34#define BITLEN_MEMORY_FILL_CHAIN     97#define BITLEN_CRC_CHANNEL_CHAIN     32/* * Buscon chain bit defintion */#define BUSCON_CPU_RESET_BIT        0#define BUSCON_CPU_FREEZE_BIT       1#define BUSCON_CPU_INT_BIT          2#define BUSCON_FORCE_CFGRST_BIT     3#define BUSCON_FORCE_NOCFGRST_BIT   4#define BUSCON_OSC_BREAK_BIT        5#define BUSCON_FORCE_BRST_BIT       6#define BUSCON_FORCE_NOBRST_BIT     7#define BUSCON_JTAG_BP_EVT_BIT      8/* * BUSTAT chain bit definition */#define BUSTAT_CPU_EXECUTING_BIT    0#define BUSTAT_DBG_ACK_BIT          1#define BUSTAT_BP_EVT_BIT           2#define BUSTAT_CPU_IN_RESET_BIT     3#define BUSTAT_BRST_STATUS_BIT      4#define BUSTAT_BCLK_STATUS_BIT      5#define BUSTAT_CFGRST_STATUS_BIT    6#define BUSTAT_END_OF_TRACE_BIT     7#define BUSTAT_CPU_RESET_BIT        8#define BUSTAT_CPU_FREEZE_BIT       9#define BUSTAT_CPU_INT_BIT         10#define BUSTAT_FORCE_CFGRST_BIT    11#define BUSTAT_FORCE_NOCFGRST_BIT  12#define BUSTAT_OSC_BREAK_BIT       13#define BUSTAT_FORCE_BRST_BIT      14#define BUSTAT_FORCE_NOBRST_BIT    15#define BUSTAT_JTAG_BP_EVT_BIT     16#endif /* _TRISCEND_A7_H */