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C51 COMPILER V7.06 AD9958 01/08/2006 12:36:01 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE AD9958
OBJECT MODULE PLACED IN AD9958.OBJ
COMPILER INVOKED BY: f:\Keil\C51\BIN\C51.EXE AD9958.C BROWSE DEBUG OBJECTEXTEND
stmt level source
1 /**********************************************
2 AD9958.C file
3 The AD9985's Operation file
4 Creat by Computer-lov Date: 2005.8.30
5 Last edit date:2005.8.30
6 Copyright(C) 2005-2015 Computer-lov
7 All rights reserved
8 ************************************************/
9 #include "AD9958.H"
10 #include <ADUC841.h>
11
12
13 //hardware connection
14
15 //#define PWR_DWN_CTL P2_0
16 #define MASTER_RESET P0_0
17 #define SDIO_3 P2_7
18 #define SDIO_2 P2_6
19 #define SDIO_1 P2_5
20 #define SDIO_0 P2_4
21 #define SCLK P0_1
22 #define CS P0_2
23
24
25
26 void delay(void)
27 {
28 1 unsigned int i;
29 1 for(i=0;i<10;i++);
30 1 }
31
32 void run(void)
33 {
34 1 //unsigned int i;
35 1 IO_UPDATA=0;
36 1 IO_UPDATA=0;
37 1 IO_UPDATA=0;
38 1 IO_UPDATA=0;
39 1 IO_UPDATA=0;
40 1 IO_UPDATA=0;
41 1 //for(i=0;i<200;i++);
42 1 IO_UPDATA=0;
43 1 IO_UPDATA=1;
44 1 // for(i=0;i<200;i++);
45 1 }
46
47 void write_a_byte(unsigned char w_data)
48 {
49 1 unsigned char i;
50 1 for(i=0;i<8;i++)
51 1 {
52 2 SDIO_0=(w_data & 0x80);
53 2 w_data<<=1;
54 2 SCLK=1;
55 2 // delay();
C51 COMPILER V7.06 AD9958 01/08/2006 12:36:01 PAGE 2
56 2 SCLK=0;
57 2 }
58 1 }
59
60 void write_CSR(unsigned char w_data)
61 {
62 1 SDIO_3=0;
63 1 CS=0;
64 1 write_a_byte(0x00); //write address 0. CSR's address is 0.
65 1 write_a_byte(w_data);
66 1 CS=1;
67 1 SDIO_3=1;
68 1 }
69
70 void write_FR1(unsigned char w_data1,unsigned char w_data2,unsigned char w_data3)
71 {
72 1 SDIO_3=0;
73 1 delay();
74 1 CS=0;
75 1 write_a_byte(0x01); //write address 1. FR1's address is 0x01
76 1 write_a_byte(w_data1);
77 1 write_a_byte(w_data2);
78 1 write_a_byte(w_data3);
79 1 CS=1;
80 1 SDIO_3=1;
81 1 }
82
83 void write_FR2(unsigned char w_data1,unsigned char w_data2)
84 {
85 1 SDIO_3=0;
86 1 CS=0;
87 1 write_a_byte(0x02); //write address 2
88 1 write_a_byte(w_data1);
89 1 write_a_byte(w_data2);
90 1 CS=1;
91 1 SDIO_3=1;
92 1 }
93
94 void write_CFR(unsigned char w_data1,unsigned char w_data2,unsigned char w_data3)
95 {
96 1 SDIO_3=0;
97 1 CS=0;
98 1 write_a_byte(0x03);
99 1 write_a_byte(w_data1);
100 1 write_a_byte(w_data2);
101 1 write_a_byte(w_data3);
102 1 CS=1;
103 1 SDIO_3=1;
104 1 }
105
106 void write_CTW0(unsigned long int F_word) //Channel Frequency Tuning Word (CTW0)
107 {
108 1 SDIO_3=0;
109 1 CS=0;
110 1 write_a_byte(0x04);
111 1 write_a_byte(((unsigned char *)(&F_word))[0]);
112 1 write_a_byte(((unsigned char *)(&F_word))[1]);
113 1 write_a_byte(((unsigned char *)(&F_word))[2]);
114 1 write_a_byte(((unsigned char *)(&F_word))[3]);
115 1 CS=1;
116 1 SDIO_3=1;
117 1 }
C51 COMPILER V7.06 AD9958 01/08/2006 12:36:01 PAGE 3
118
119 void write_CPW0(unsigned int P_word) //Channel Phase1 Offset Word (CPW0) (0x05)
120 {
121 1 SDIO_3=0;
122 1 CS=0;
123 1 write_a_byte(0x05);
124 1 write_a_byte(((unsigned char *)(&P_word))[0]);
125 1 write_a_byte((((unsigned char *)(&P_word))[1])&0x3F);
126 1 CS=1;
127 1 SDIO_3=1;
128 1 }
129
130 void write_ACR(unsigned long int A_word)
131 {
132 1 SDIO_3=0;
133 1 CS=0;
134 1 write_a_byte(0x06);
135 1 write_a_byte(((unsigned char *)(&A_word))[1]);
136 1 write_a_byte(((unsigned char *)(&A_word))[2]);
137 1 write_a_byte(((unsigned char *)(&A_word))[3]);
138 1 CS=1;
139 1 SDIO_3=1;
140 1 }
141
142 void write_LSR(unsigned char rising,unsigned char falling)
143 {
144 1 SDIO_3=0;
145 1 CS=0;
146 1 write_a_byte(0x07);
147 1 write_a_byte(rising);
148 1 write_a_byte(falling);
149 1 CS=1;
150 1 SDIO_3=1;
151 1 }
152
153 void write_RDW(unsigned long rising)
154 {
155 1 SDIO_3=0;
156 1 CS=0;
157 1 write_a_byte(0x08);
158 1 write_a_byte(((unsigned char *)(&rising))[0]);
159 1 write_a_byte(((unsigned char *)(&rising))[1]);
160 1 write_a_byte(((unsigned char *)(&rising))[2]);
161 1 write_a_byte(((unsigned char *)(&rising))[3]);
162 1 CS=1;
163 1 SDIO_3=1;
164 1 }
165
166 void write_FDW(unsigned long falling)
167 {
168 1 SDIO_3=0;
169 1 CS=0;
170 1 write_a_byte(0x09);
171 1 write_a_byte(((unsigned char *)(&falling))[0]);
172 1 write_a_byte(((unsigned char *)(&falling))[1]);
173 1 write_a_byte(((unsigned char *)(&falling))[2]);
174 1 write_a_byte(((unsigned char *)(&falling))[3]);
175 1 CS=1;
176 1 SDIO_3=1;
177 1 }
178
179 void write_CTWn(unsigned char n,unsigned long int w_data)
C51 COMPILER V7.06 AD9958 01/08/2006 12:36:01 PAGE 4
180 {
181 1 SDIO_3=0;
182 1 CS=0;
183 1 write_a_byte(n+0x09); //CTWn's address is n+0x09.n>=1 and n<=15.
184 1 write_a_byte(((unsigned char *)(&w_data))[0]);
185 1 write_a_byte(((unsigned char *)(&w_data))[1]);
186 1 write_a_byte(((unsigned char *)(&w_data))[2]);
187 1 write_a_byte(((unsigned char *)(&w_data))[3]);
188 1 CS=1;
189 1 SDIO_3=1;
190 1 }
191
192 #define PLL_DIV 5
193 #define systemp_frequency (22.1184*1000000*PLL_DIV)
194
195 void set_frequency(unsigned long int f)
196 {
197 1 unsigned long int temp;
198 1 temp=(unsigned long int)f*(0xFFFFFFFF/(float)systemp_frequency+1.0/systemp_frequency);
199 1 write_CTW0(temp);
200 1 }
201
202
203 unsigned long int change(unsigned long int f)
204 {
205 1 unsigned long int temp;
206 1 temp=(unsigned long int)f*(0xFFFFFFFF/(float)systemp_frequency+1.0/systemp_frequency);
207 1 return temp;
208 1 }
209
210 void AD9958_init(void)
211 {
212 1 unsigned int i;
213 1 // PWR_DWN_CTL=0;
214 1 MASTER_RESET=0;
215 1 for(i=0;i<10000;i++);
216 1 CS=1;
217 1 SCLK=0;
218 1 SDIO_3=1;
219 1 MASTER_RESET=1;
220 1 for(i=0;i<10000;i++);
221 1 MASTER_RESET=0;
222 1 for(i=0;i<100;i++);
223 1 delay();
224 1 write_CSR(0xF0); //70
225 1
226 1 write_FR1(0x14,0x50,0x00);
227 1 write_FR2(0x00,0x00);
228 1 write_CFR(0x00,0x03,0x00); //no modulation
229 1 // write_CFR(0xc0,0x03,0x00); //auto sweep,AM
230 1 // write_CTW0(0x7ff00000);
231 1 //set_frequency(10000000);
232 1 write_CPW0(0x00);
233 1 // write_ACR(0x00);
234 1 // write_ACR(0xFF03FF);
235 1 write_LSR(0xFF,0xFF);
236 1 write_RDW(0x0ff00000);
237 1 write_FDW(0x0ff00000);
238 1 write_CTWn(1,0x7E000000);
239 1
240 1 // modulated signal
241 1 write_CSR(0x70); //70
C51 COMPILER V7.06 AD9958 01/08/2006 12:36:01 PAGE 5
242 1 set_frequency(1000);
243 1 write_ACR(0xff13af); //0x3af 100% modulation
244 1
245 1
246 1 //調(diào)幅載波
247 1 write_CSR(0x80);
248 1 write_ACR(0xff10ff);
249 1 set_frequency(10000000);
250 1
251 1
252 1 run();
253 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 607 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- 23
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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