case CSR_SPLIT_TIMEOUT_HI:                host->csr.split_timeout_hi =                         be32_to_cpu(*(data++)) & 0x00000007;		calculate_expire(&host->csr);                out;        case CSR_SPLIT_TIMEOUT_LO:                host->csr.split_timeout_lo =                         be32_to_cpu(*(data++)) & 0xfff80000;		calculate_expire(&host->csr);                out;                /* address gap */                return RCODE_ADDRESS_ERROR;        case CSR_CYCLE_TIME:                /* should only be set by cycle start packet, automatically */                host->csr.cycle_time = be32_to_cpu(*data);                host->driver->devctl(host, SET_CYCLE_COUNTER,                                       be32_to_cpu(*(data++)));                out;        case CSR_BUS_TIME:                host->csr.bus_time = be32_to_cpu(*(data++)) & 0xffffff80;                out;                /* address gap */                return RCODE_ADDRESS_ERROR;        case CSR_BUSY_TIMEOUT:                /* not yet implemented */                return RCODE_ADDRESS_ERROR;        case CSR_BUS_MANAGER_ID:        case CSR_BANDWIDTH_AVAILABLE:        case CSR_CHANNELS_AVAILABLE_HI:        case CSR_CHANNELS_AVAILABLE_LO:                /* these are not writable, only lockable */                return RCODE_TYPE_ERROR;	case CSR_BROADCAST_CHANNEL:		/* only the valid bit can be written */		host->csr.broadcast_channel = (host->csr.broadcast_channel & ~0x40000000)                        | (be32_to_cpu(*data) & 0x40000000);		out;                /* address gap to end - fall through */        default:                return RCODE_ADDRESS_ERROR;        }        return RCODE_COMPLETE;}#undef outstatic int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store,                     u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl){        int csraddr = addr - CSR_REGISTER_BASE;        unsigned long flags;        quadlet_t *regptr = NULL;        if (csraddr & 0x3)		return RCODE_TYPE_ERROR;        if (csraddr < CSR_BUS_MANAGER_ID || csraddr > CSR_CHANNELS_AVAILABLE_LO            || extcode != EXTCODE_COMPARE_SWAP)                goto unsupported_lockreq;        data = be32_to_cpu(data);        arg = be32_to_cpu(arg);	/* Is somebody releasing the broadcast_channel on us? */	if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x1)) {		/* Note: this is may not be the right way to handle		 * the problem, so we should look into the proper way		 * eventually. */		HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "			  "broadcast channel 31.  Ignoring.",			  NODE_BUS_ARGS(host, nodeid));		data &= ~0x1;	/* keep broadcast channel allocated */	}        if (host->driver->hw_csr_reg) {                quadlet_t old;                old = host->driver->                        hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,                                   data, arg);                *store = cpu_to_be32(old);                return RCODE_COMPLETE;        }        spin_lock_irqsave(&host->csr.lock, flags);        switch (csraddr) {        case CSR_BUS_MANAGER_ID:                regptr = &host->csr.bus_manager_id;		*store = cpu_to_be32(*regptr);		if (*regptr == arg)			*regptr = data;                break;        case CSR_BANDWIDTH_AVAILABLE:        {                quadlet_t bandwidth;                quadlet_t old;                quadlet_t new;                regptr = &host->csr.bandwidth_available;                old = *regptr;                /* bandwidth available algorithm adapted from IEEE 1394a-2000 spec */                if (arg > 0x1fff) {                        *store = cpu_to_be32(old);	/* change nothing */			break;                }                data &= 0x1fff;                if (arg >= data) {                        /* allocate bandwidth */                        bandwidth = arg - data;                        if (old >= bandwidth) {                                new = old - bandwidth;                                *store = cpu_to_be32(arg);                                *regptr = new;                        } else {                                *store = cpu_to_be32(old);                        }                } else {                        /* deallocate bandwidth */                        bandwidth = data - arg;                        if (old + bandwidth < 0x2000) {                                new = old + bandwidth;                                *store = cpu_to_be32(arg);                                *regptr = new;                        } else {                                *store = cpu_to_be32(old);                        }                }                break;        }        case CSR_CHANNELS_AVAILABLE_HI:        {                /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */                quadlet_t affected_channels = arg ^ data;                regptr = &host->csr.channels_available_hi;                if ((arg & affected_channels) == (*regptr & affected_channels)) {                        *regptr ^= affected_channels;                        *store = cpu_to_be32(arg);                } else {                        *store = cpu_to_be32(*regptr);                }                break;        }        case CSR_CHANNELS_AVAILABLE_LO:        {                /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */                quadlet_t affected_channels = arg ^ data;                regptr = &host->csr.channels_available_lo;                if ((arg & affected_channels) == (*regptr & affected_channels)) {                        *regptr ^= affected_channels;                        *store = cpu_to_be32(arg);                } else {                        *store = cpu_to_be32(*regptr);                }                break;        }        }        spin_unlock_irqrestore(&host->csr.lock, flags);        return RCODE_COMPLETE; unsupported_lockreq:        switch (csraddr) {        case CSR_STATE_CLEAR:        case CSR_STATE_SET:        case CSR_RESET_START:        case CSR_NODE_IDS:        case CSR_SPLIT_TIMEOUT_HI:        case CSR_SPLIT_TIMEOUT_LO:        case CSR_CYCLE_TIME:        case CSR_BUS_TIME:	case CSR_BROADCAST_CHANNEL:                return RCODE_TYPE_ERROR;        case CSR_BUSY_TIMEOUT:                /* not yet implemented - fall through */        default:                return RCODE_ADDRESS_ERROR;        }}static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store,		       u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl){	int csraddr = addr - CSR_REGISTER_BASE;	unsigned long flags;	data = be64_to_cpu(data);	arg = be64_to_cpu(arg);	if (csraddr & 0x3)		return RCODE_TYPE_ERROR;	if (csraddr != CSR_CHANNELS_AVAILABLE	    || extcode != EXTCODE_COMPARE_SWAP)		goto unsupported_lock64req;	/* Is somebody releasing the broadcast_channel on us? */	if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x100000000ULL)) {		/* Note: this is may not be the right way to handle		 * the problem, so we should look into the proper way                 * eventually. */		HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "			  "broadcast channel 31.  Ignoring.",			  NODE_BUS_ARGS(host, nodeid));		data &= ~0x100000000ULL;	/* keep broadcast channel allocated */	}	if (host->driver->hw_csr_reg) {		quadlet_t data_hi, data_lo;		quadlet_t arg_hi, arg_lo;		quadlet_t old_hi, old_lo;		data_hi = data >> 32;		data_lo = data & 0xFFFFFFFF;		arg_hi = arg >> 32;		arg_lo = arg & 0xFFFFFFFF;		old_hi = host->driver->hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,                                                  data_hi, arg_hi);		old_lo = host->driver->hw_csr_reg(host, ((csraddr + 4) - CSR_BUS_MANAGER_ID) >> 2,                                                  data_lo, arg_lo);		*store = cpu_to_be64(((octlet_t)old_hi << 32) | old_lo);	} else {		octlet_t old;		octlet_t affected_channels = arg ^ data;		spin_lock_irqsave(&host->csr.lock, flags);		old = ((octlet_t)host->csr.channels_available_hi << 32) | host->csr.channels_available_lo;		if ((arg & affected_channels) == (old & affected_channels)) {			host->csr.channels_available_hi ^= (affected_channels >> 32);			host->csr.channels_available_lo ^= (affected_channels & 0xffffffff);			*store = cpu_to_be64(arg);		} else {			*store = cpu_to_be64(old);		}		spin_unlock_irqrestore(&host->csr.lock, flags);	}	/* Is somebody erroneously releasing the broadcast_channel on us? */	if (host->csr.channels_available_hi & 0x1)		host->csr.channels_available_hi &= ~0x1;	return RCODE_COMPLETE; unsupported_lock64req:	switch (csraddr) {	case CSR_STATE_CLEAR:	case CSR_STATE_SET:	case CSR_RESET_START:	case CSR_NODE_IDS:	case CSR_SPLIT_TIMEOUT_HI:	case CSR_SPLIT_TIMEOUT_LO:	case CSR_CYCLE_TIME:	case CSR_BUS_TIME:	case CSR_BUS_MANAGER_ID:	case CSR_BROADCAST_CHANNEL:	case CSR_BUSY_TIMEOUT:	case CSR_BANDWIDTH_AVAILABLE:		return RCODE_TYPE_ERROR;	default:		return RCODE_ADDRESS_ERROR;	}}static int write_fcp(struct hpsb_host *host, int nodeid, int dest,		     quadlet_t *data, u64 addr, size_t length, u16 flags){        int csraddr = addr - CSR_REGISTER_BASE;        if (length > 512)                return RCODE_TYPE_ERROR;        switch (csraddr) {        case CSR_FCP_COMMAND:                highlevel_fcp_request(host, nodeid, 0, (u8 *)data, length);                break;        case CSR_FCP_RESPONSE:                highlevel_fcp_request(host, nodeid, 1, (u8 *)data, length);                break;        default:                return RCODE_TYPE_ERROR;        }        return RCODE_COMPLETE;}static struct hpsb_highlevel csr_highlevel = {	.name =		"standard registers",	.add_host =	add_host,        .host_reset =	host_reset,};static struct hpsb_address_ops map_ops = {        .read = read_maps,};static struct hpsb_address_ops fcp_ops = {        .write = write_fcp,};static struct hpsb_address_ops reg_ops = {        .read = read_regs,        .write = write_regs,        .lock = lock_regs,	.lock64 = lock64_regs,};void init_csr(void){	hpsb_register_highlevel(&csr_highlevel);        hpsb_register_addrspace(&csr_highlevel, &reg_ops, CSR_REGISTER_BASE,                                CSR_REGISTER_BASE + CSR_CONFIG_ROM);        hpsb_register_addrspace(&csr_highlevel, &map_ops,                                 CSR_REGISTER_BASE + CSR_CONFIG_ROM,                                CSR_REGISTER_BASE + CSR_CONFIG_ROM_END);        if (fcp) {		hpsb_register_addrspace(&csr_highlevel, &fcp_ops,                                CSR_REGISTER_BASE + CSR_FCP_COMMAND,                                CSR_REGISTER_BASE + CSR_FCP_END);	}        hpsb_register_addrspace(&csr_highlevel, &map_ops,                                CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP,                                CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP_END);        hpsb_register_addrspace(&csr_highlevel, &map_ops,                                CSR_REGISTER_BASE + CSR_SPEED_MAP,                                CSR_REGISTER_BASE + CSR_SPEED_MAP_END);}void cleanup_csr(void){        hpsb_unregister_highlevel(&csr_highlevel);}