/* * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver * *  Copyright (c) 2005, Advanced Micro Devices, Inc. * *  Developed with help from the 2.4.30 MMC AU1XXX controller including *  the following copyright notices: *     Copyright (c) 2003-2004 Embedded Edge, LLC. *     Portions Copyright (C) 2002 Embedix, Inc *     Copyright 2002 Hewlett-Packard Company *  2.6 version of this driver inspired by: *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman, *     All Rights Reserved. *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King, *     All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. *//* Why is a timer used to detect insert events? * * From the AU1100 MMC application guide: * If the Au1100-based design is intended to support both MultiMediaCards * and 1- or 4-data bit SecureDigital cards, then the solution is to * connect a weak (560KOhm) pull-up resistor to connector pin 1. * In doing so, a MMC card never enters SPI-mode communications, * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective * (the low to high transition will not occur). * * So we use the timer to check the status manually. */#include <linux/config.h>#include <linux/module.h>#include <linux/init.h>#include <linux/platform_device.h>#include <linux/mm.h>#include <linux/interrupt.h>#include <linux/dma-mapping.h>#include <linux/mmc/host.h>#include <linux/mmc/protocol.h>#include <asm/io.h>#include <asm/mach-au1x00/au1000.h>#include <asm/mach-au1x00/au1xxx_dbdma.h>#include <asm/mach-au1x00/au1100_mmc.h>#include <asm/scatterlist.h>#include <au1xxx.h>#include "au1xmmc.h"#define DRIVER_NAME "au1xxx-mmc"/* Set this to enable special debugging macros *//* #define MMC_DEBUG */#ifdef MMC_DEBUG#define DEBUG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)#else#define DEBUG(fmt, idx, args...)#endifconst struct {	u32 iobase;	u32 tx_devid, rx_devid;	u16 bcsrpwr;	u16 bcsrstatus;	u16 wpstatus;} au1xmmc_card_table[] = {	{ SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,	  BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },#ifndef CONFIG_MIPS_DB1200	{ SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,	  BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }#endif};#define AU1XMMC_CONTROLLER_COUNT \	(sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))/* This array stores pointers for the hosts (used by the IRQ handler) */struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];static int dma = 1;#ifdef MODULEMODULE_PARM(dma, "i");MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");#endifstatic inline void IRQ_ON(struct au1xmmc_host *host, u32 mask){	u32 val = au_readl(HOST_CONFIG(host));	val |= mask;	au_writel(val, HOST_CONFIG(host));	au_sync();}static inline void FLUSH_FIFO(struct au1xmmc_host *host){	u32 val = au_readl(HOST_CONFIG2(host));	au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));	au_sync_delay(1);	/* SEND_STOP will turn off clock control - this re-enables it */	val &= ~SD_CONFIG2_DF;	au_writel(val, HOST_CONFIG2(host));	au_sync();}static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask){	u32 val = au_readl(HOST_CONFIG(host));	val &= ~mask;	au_writel(val, HOST_CONFIG(host));	au_sync();}static inline void SEND_STOP(struct au1xmmc_host *host){	/* We know the value of CONFIG2, so avoid a read we don't need */	u32 mask = SD_CONFIG2_EN;	WARN_ON(host->status != HOST_S_DATA);	host->status = HOST_S_STOP;	au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));	au_sync();	/* Send the stop commmand */	au_writel(STOP_CMD, HOST_CMD(host));}static void au1xmmc_set_power(struct au1xmmc_host *host, int state){	u32 val = au1xmmc_card_table[host->id].bcsrpwr;	bcsr->board &= ~val;	if (state) bcsr->board |= val;	au_sync_delay(1);}static inline int au1xmmc_card_inserted(struct au1xmmc_host *host){	return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)		? 1 : 0;}static inline int au1xmmc_card_readonly(struct au1xmmc_host *host){	return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)		? 1 : 0;}static void au1xmmc_finish_request(struct au1xmmc_host *host){	struct mmc_request *mrq = host->mrq;	host->mrq = NULL;	host->flags &= HOST_F_ACTIVE;	host->dma.len = 0;	host->dma.dir = 0;	host->pio.index  = 0;	host->pio.offset = 0;	host->pio.len = 0;	host->status = HOST_S_IDLE;	bcsr->disk_leds |= (1 << 8);	mmc_request_done(host->mmc, mrq);}static void au1xmmc_tasklet_finish(unsigned long param){	struct au1xmmc_host *host = (struct au1xmmc_host *) param;	au1xmmc_finish_request(host);}static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,				struct mmc_command *cmd){	u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);	switch (mmc_resp_type(cmd)) {	case MMC_RSP_R1:		mmccmd |= SD_CMD_RT_1;		break;	case MMC_RSP_R1B:		mmccmd |= SD_CMD_RT_1B;		break;	case MMC_RSP_R2:		mmccmd |= SD_CMD_RT_2;		break;	case MMC_RSP_R3:		mmccmd |= SD_CMD_RT_3;		break;	}	switch(cmd->opcode) {	case MMC_READ_SINGLE_BLOCK:	case SD_APP_SEND_SCR:		mmccmd |= SD_CMD_CT_2;		break;	case MMC_READ_MULTIPLE_BLOCK:		mmccmd |= SD_CMD_CT_4;		break;	case MMC_WRITE_BLOCK:		mmccmd |= SD_CMD_CT_1;		break;	case MMC_WRITE_MULTIPLE_BLOCK:		mmccmd |= SD_CMD_CT_3;		break;	case MMC_STOP_TRANSMISSION:		mmccmd |= SD_CMD_CT_7;		break;	}	au_writel(cmd->arg, HOST_CMDARG(host));	au_sync();	if (wait)		IRQ_OFF(host, SD_CONFIG_CR);	au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));	au_sync();	/* Wait for the command to go on the line */	while(1) {		if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))			break;	}	/* Wait for the command to come back */	if (wait) {		u32 status = au_readl(HOST_STATUS(host));		while(!(status & SD_STATUS_CR))			status = au_readl(HOST_STATUS(host));		/* Clear the CR status */		au_writel(SD_STATUS_CR, HOST_STATUS(host));		IRQ_ON(host, SD_CONFIG_CR);	}	return MMC_ERR_NONE;}static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status){	struct mmc_request *mrq = host->mrq;	struct mmc_data *data;	u32 crc;	WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);	if (host->mrq == NULL)		return;	data = mrq->cmd->data;	if (status == 0)		status = au_readl(HOST_STATUS(host));	/* The transaction is really over when the SD_STATUS_DB bit is clear */	while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))		status = au_readl(HOST_STATUS(host));	data->error = MMC_ERR_NONE;	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);        /* Process any errors */	crc = (status & (SD_STATUS_WC | SD_STATUS_RC));	if (host->flags & HOST_F_XMIT)		crc |= ((status & 0x07) == 0x02) ? 0 : 1;	if (crc)		data->error = MMC_ERR_BADCRC;	/* Clear the CRC bits */	au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));	data->bytes_xfered = 0;	if (data->error == MMC_ERR_NONE) {		if (host->flags & HOST_F_DMA) {			u32 chan = DMA_CHANNEL(host);			chan_tab_t *c = *((chan_tab_t **) chan);			au1x_dma_chan_t *cp = c->chan_ptr;			data->bytes_xfered = cp->ddma_bytecnt;		}		else			data->bytes_xfered =				(data->blocks * (1 << data->blksz_bits)) -				host->pio.len;	}	au1xmmc_finish_request(host);}static void au1xmmc_tasklet_data(unsigned long param){	struct au1xmmc_host *host = (struct au1xmmc_host *) param;	u32 status = au_readl(HOST_STATUS(host));	au1xmmc_data_complete(host, status);}#define AU1XMMC_MAX_TRANSFER 8static void au1xmmc_send_pio(struct au1xmmc_host *host){	struct mmc_data *data = 0;	int sg_len, max, count = 0;	unsigned char *sg_ptr;	u32 status = 0;	struct scatterlist *sg;	data = host->mrq->data;	if (!(host->flags & HOST_F_XMIT))		return;	/* This is the pointer to the data buffer */	sg = &data->sg[host->pio.index];	sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;	/* This is the space left inside the buffer */	sg_len = data->sg[host->pio.index].length - host->pio.offset;	/* Check to if we need less then the size of the sg_buffer */	max = (sg_len > host->pio.len) ? host->pio.len : sg_len;	if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;	for(count = 0; count < max; count++ ) {		unsigned char val;		status = au_readl(HOST_STATUS(host));		if (!(status & SD_STATUS_TH))			break;		val = *sg_ptr++;		au_writel((unsigned long) val, HOST_TXPORT(host));		au_sync();	}	host->pio.len -= count;	host->pio.offset += count;	if (count == sg_len) {		host->pio.index++;		host->pio.offset = 0;	}	if (host->pio.len == 0) {		IRQ_OFF(host, SD_CONFIG_TH);		if (host->flags & HOST_F_STOP)			SEND_STOP(host);		tasklet_schedule(&host->data_task);	}}static void au1xmmc_receive_pio(struct au1xmmc_host *host){	struct mmc_data *data = 0;	int sg_len = 0, max = 0, count = 0;	unsigned char *sg_ptr = 0;	u32 status = 0;	struct scatterlist *sg;	data = host->mrq->data;	if (!(host->flags & HOST_F_RECV))		return;	max = host->pio.len;	if (host->pio.index < host->dma.len) {		sg = &data->sg[host->pio.index];		sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;		/* This is the space left inside the buffer */		sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;		/* Check to if we need less then the size of the sg_buffer */		if (sg_len < max) max = sg_len;	}	if (max > AU1XMMC_MAX_TRANSFER)		max = AU1XMMC_MAX_TRANSFER;	for(count = 0; count < max; count++ ) {		u32 val;		status = au_readl(HOST_STATUS(host));		if (!(status & SD_STATUS_NE))			break;		if (status & SD_STATUS_RC) {			DEBUG("RX CRC Error [%d + %d].\n", host->id,					host->pio.len, count);			break;		}		if (status & SD_STATUS_RO) {			DEBUG("RX Overrun [%d + %d]\n", host->id,					host->pio.len, count);			break;		}		else if (status & SD_STATUS_RU) {			DEBUG("RX Underrun [%d + %d]\n", host->id,					host->pio.len,	count);			break;		}		val = au_readl(HOST_RXPORT(host));		if (sg_ptr)			*sg_ptr++ = (unsigned char) (val & 0xFF);	}	host->pio.len -= count;	host->pio.offset += count;	if (sg_len && count == sg_len) {		host->pio.index++;		host->pio.offset = 0;	}	if (host->pio.len == 0) {		//IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);		IRQ_OFF(host, SD_CONFIG_NE);		if (host->flags & HOST_F_STOP)			SEND_STOP(host);		tasklet_schedule(&host->data_task);	}}/* static void au1xmmc_cmd_complete   This is called when a command has been completed - grab the response   and check for errors.  Then start the data transfer if it is indicated.*/static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status){	struct mmc_request *mrq = host->mrq;	struct mmc_command *cmd;	int trans;	if (!host->mrq)		return;	cmd = mrq->cmd;	cmd->error = MMC_ERR_NONE;	if (cmd->flags & MMC_RSP_PRESENT) {		if (cmd->flags & MMC_RSP_136) {			u32 r[4];			int i;			r[0] = au_readl(host->iobase + SD_RESP3);			r[1] = au_readl(host->iobase + SD_RESP2);			r[2] = au_readl(host->iobase + SD_RESP1);			r[3] = au_readl(host->iobase + SD_RESP0);			/* The CRC is omitted from the response, so really			 * we only got 120 bytes, but the engine expects			 * 128 bits, so we have to shift things up			 */			for(i = 0; i < 4; i++) {				cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;				if (i != 3)					cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;			}		} else {			/* Techincally, we should be getting all 48 bits of			 * the response (SD_RESP1 + SD_RESP2), but because			 * our response omits the CRC, our data ends up			 * being shifted 8 bits to the right.  In this case,			 * that means that the OSR data starts at bit 31,			 * so we can just read RESP0 and return that			 */			cmd->resp[0] = au_readl(host->iobase + SD_RESP0);