module test;
reg clk,nRst;
reg [15:0]dout,nFrameo,nValido,din,nFrame,nValid;

router_sys router_sys1(.dout(dout), .nFrameo(nFrameo), .nValido(nValido), 
           .din(din), .nFrame(nFrame), .nValid(nValid), .clk(clk), .nRst(nRst));
//assign din=din_t;

task apply_input;
input [7:0]data;
input [3:0]address;
input [3:0]port;
integer i;
reg  [16:0]data_t;


//initial 
begin
    data_t={address[3:0],5'b11111,data[7:0]};
    nFrame[port]=1;
    i=16;
    #25  nFrame[port]=0;
        @(posedge clk); 

        repeat(17) begin
         @(posedge clk); 
         
            din[port]=data_t[i];
                if(i>=8)
            nValid[port]=1;
          else if (i>=0) 
       nValid[port]=$random; 
        else 
          i=16;
   

    i=i-1;
            end

    #1700 nFrame[port]=1;
end

            
endtask




always  begin
   clk=0;
   #50 clk=1;
   #50 clk=0;
        end

initial begin
       nFrame=16'b1111_1111_1111_1111;
       nRst=1;
  #50  nRst=0;
  #150 nRst=1;
apply_input(8'b1001_1110, 4'b1111,4'b0000);
apply_input(8'b1001_1110, 4'b1110,4'b0001);
apply_input(8'b1001_1110, 4'b1101,4'b0010);
apply_input(8'b1001_1110, 4'b1100,4'b0011);
apply_input(8'b1001_1110, 4'b1011,4'b0100);
apply_input(8'b1001_1110, 4'b1010,4'b0101);
apply_input(8'b1001_1110, 4'b1001,4'b0110);
apply_input(8'b1001_1110, 4'b1000,4'b0111);
apply_input(8'b1001_1110, 4'b0111,4'b1000);
apply_input(8'b1001_1110, 4'b0110,4'b1001);
apply_input(8'b1001_1110, 4'b0101,4'b1010);
apply_input(8'b1001_1110, 4'b0100,4'b1011);
apply_input(8'b1001_1110, 4'b0011,4'b1100);
apply_input(8'b1001_1110, 4'b0010,4'b1101);
apply_input(8'b1001_1110, 4'b0001,4'b1110);
apply_input(8'b1001_1110, 4'b0000,4'b1111);
#5000 $finish;
end

initial begin
$vcdplusfile("debug.vpd");
$vcdpluson; 
end
endmodule