library ieee;use ieee.std_logic_1164.all;entity reg isgeneric (n : natural := 32);port (D : in std_logic_vector(31 downto 0);Clock, Reset, Enable : in std_logic;Q : out std_logic_vector(31 downto 0));end entity reg;architecture behavioural of reg isbeginp0: process (Clock, Reset) isbeginif (Reset = '0') thenQ <= (others => '0');elsif rising_edge(Clock) thenif Enable = '1' thenQ <= D;end if;end if;end process p0;end architecture behavioural;