Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
    Info: Processing started: Sun Mar 30 20:52:19 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_TV -c DE2_TV
Info: Found 1 design units, including 1 entities, in source file DE2_TV2.v
    Info: Found entity 1: DE2_TV2
Info: Found 1 design units, including 1 entities, in source file write_FIFO1.v
    Info: Found entity 1: write_FIFO1
Info: Found 1 design units, including 1 entities, in source file DE2_TV1.v
    Info: Found entity 1: DE2_TV1
Info: Found 1 design units, including 1 entities, in source file TP_RAM.v
    Info: Found entity 1: TP_RAM
Info: Found 1 design units, including 1 entities, in source file DIV.v
    Info: Found entity 1: DIV
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_RD_FIFO.v
    Info: Found entity 1: Sdram_RD_FIFO
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_WR_FIFO.v
    Info: Found entity 1: Sdram_WR_FIFO
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/command.v
    Info: Found entity 1: command
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/control_interface.v
    Info: Found entity 1: control_interface
Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(26): truncated literal to match 1 bits
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/sdr_data_path.v
    Info: Found entity 1: sdr_data_path
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_Control_4Port.v
    Info: Found entity 1: Sdram_Control_4Port
Info: Found 1 design units, including 1 entities, in source file Sdram_Control_4Port/Sdram_PLL.v
    Info: Found entity 1: Sdram_PLL
Info: Found 1 design units, including 1 entities, in source file MAC_3.v
    Info: Found entity 1: MAC_3
Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v
    Info: Found entity 1: Reset_Delay
Warning (10229): Verilog HDL Expression warning at YCbCr2RGB.v(124): truncated literal to match 17 bits
Info: Found 1 design units, including 1 entities, in source file YCbCr2RGB.v
    Info: Found entity 1: YCbCr2RGB
Warning (10238): Verilog Module Declaration warning at DE2_TV.v(34): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "DE2_TV"
Info: Found 1 design units, including 1 entities, in source file DE2_TV.v
    Info: Found entity 1: DE2_TV
Info: Found 1 design units, including 1 entities, in source file I2C_AV_Config.v
    Info: Found entity 1: I2C_AV_Config
Info: Found 1 design units, including 1 entities, in source file I2C_Controller.v
    Info: Found entity 1: I2C_Controller
Info: Found 1 design units, including 1 entities, in source file PLL.v
    Info: Found entity 1: PLL
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v
    Info: Found entity 1: SEG7_LUT
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_8.v
    Info: Found entity 1: SEG7_LUT_8
Info: Found 1 design units, including 1 entities, in source file YUV422_to_444.v
    Info: Found entity 1: YUV422_to_444
Info: Found 1 design units, including 1 entities, in source file TD_Detect.v
    Info: Found entity 1: TD_Detect
Info: Found 1 design units, including 1 entities, in source file ITU_656_Decoder.v
    Info: Found entity 1: ITU_656_Decoder
Info: Found 1 design units, including 1 entities, in source file VGA_Ctrl.v
    Info: Found entity 1: VGA_Ctrl
Warning: Can't analyze file -- file D:/DE2_TV_m_write/avar.v is missing
Info: Elaborating entity "DE2_TV" for the top level hierarchy
Warning (10034): Output port "DRAM_CLK" at DE2_TV.v(61) has no driver
Warning: Using design file SDRAM_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SDRAM_PLL
Info: Elaborating entity "SDRAM_PLL" for hierarchy "SDRAM_PLL:PLL1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "SDRAM_PLL:PLL1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "SDRAM_PLL:PLL1|altpll:altpll_component"
Warning: Using design file system_Reset.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: system_Reset
Info: Elaborating entity "system_Reset" for hierarchy "system_Reset:rst"
Warning (10230): Verilog HDL assignment warning at system_Reset.v(10): truncated value with size 32 to match size of target (16)
Warning: Using design file avl_m_w.v, which is not specified as a design file for the current project, but contains definitions for 10 design units and 10 entities in project
    Info: Found entity 1: cpu_0_jtag_debug_module_arbitrator
    Info: Found entity 2: cpu_0_data_master_arbitrator
    Info: Found entity 3: cpu_0_instruction_master_arbitrator
    Info: Found entity 4: de2_tv2_0_avalon_master_0_arbitrator
    Info: Found entity 5: avl_m_w_reset_clk_domain_synch_module
    Info: Found entity 6: jtag_uart_0_avalon_jtag_slave_arbitrator
    Info: Found entity 7: rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module
    Info: Found entity 8: rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module
    Info: Found entity 9: sdram_0_s1_arbitrator
    Info: Found entity 10: avl_m_w
Info: Elaborating entity "avl_m_w" for hierarchy "avl_m_w:DUT"
Info: Elaborating entity "cpu_0_jtag_debug_module_arbitrator" for hierarchy "avl_m_w:DUT|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module"
Info: Elaborating entity "cpu_0_data_master_arbitrator" for hierarchy "avl_m_w:DUT|cpu_0_data_master_arbitrator:the_cpu_0_data_master"
Info: Elaborating entity "cpu_0_instruction_master_arbitrator" for hierarchy "avl_m_w:DUT|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master"
Warning: Using design file cpu_0.v, which is not specified as a design file for the current project, but contains definitions for 29 design units and 29 entities in project
    Info: Found entity 1: cpu_0_ic_data_module
    Info: Found entity 2: cpu_0_ic_tag_module
    Info: Found entity 3: cpu_0_bht_module
    Info: Found entity 4: cpu_0_register_bank_a_module
    Info: Found entity 5: cpu_0_register_bank_b_module
    Info: Found entity 6: cpu_0_dc_tag_module
    Info: Found entity 7: cpu_0_dc_data_module
    Info: Found entity 8: cpu_0_nios2_oci_debug
    Info: Found entity 9: cpu_0_ociram_lpm_dram_bdp_component_module
    Info: Found entity 10: cpu_0_nios2_ocimem
    Info: Found entity 11: cpu_0_nios2_avalon_reg
    Info: Found entity 12: cpu_0_nios2_oci_break
    Info: Found entity 13: cpu_0_nios2_oci_xbrk
    Info: Found entity 14: cpu_0_nios2_oci_match_paired
    Info: Found entity 15: cpu_0_nios2_oci_match_single
    Info: Found entity 16: cpu_0_nios2_oci_dbrk
    Info: Found entity 17: cpu_0_nios2_oci_itrace
    Info: Found entity 18: cpu_0_nios2_oci_td_mode
    Info: Found entity 19: cpu_0_nios2_oci_dtrace
    Info: Found entity 20: cpu_0_nios2_oci_compute_tm_count
    Info: Found entity 21: cpu_0_nios2_oci_fifowp_inc
    Info: Found entity 22: cpu_0_nios2_oci_fifocount_inc
    Info: Found entity 23: cpu_0_nios2_oci_fifo
    Info: Found entity 24: cpu_0_nios2_oci_pib
    Info: Found entity 25: cpu_0_traceram_lpm_dram_bdp_component_module
    Info: Found entity 26: cpu_0_nios2_oci_im
    Info: Found entity 27: cpu_0_nios2_performance_monitors
    Info: Found entity 28: cpu_0_nios2_oci
    Info: Found entity 29: cpu_0
Info: Elaborating entity "cpu_0" for hierarchy "avl_m_w:DUT|cpu_0:the_cpu_0"
Warning: Using design file cpu_0_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cpu_0_test_bench
Info: Elaborating entity "cpu_0_test_bench" for hierarchy "avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench"
Info: Elaborating entity "cpu_0_ic_data_module" for hierarchy "avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data"
Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sbf1.tdf
    Info: Found entity 1: altsyncram_sbf1
Info: Elaborating entity "altsyncram_sbf1" for hierarchy "avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sbf1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_k1l1.tdf
    Info: Found entity 1: altsyncram_k1l1
Info: Elaborating entity "altsyncram_k1l1" for hierarchy "avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_sbf1:auto_generated|altsyncram_k1l1:altsyncram1"
Info: Elaborating entity "cpu_0_ic_tag_module" for hierarchy "avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag"
Info: Elaborating entity "altsyncram" for hierarchy "avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "avl_m_w:DUT|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram"