module count_16 (clk, reset, enable, q);

input clk, reset, enable;
output [15:0] q;

reg [15:0] q;
//在四個數碼管上分別顯示時分秒，最低秒位計滿9時進1，次低位計滿5時進1；當秒位計滿59秒時進1，分位開始計數
//四個數碼管顯示分秒分別對應16位計數器的計數值（每4位一組）
always @ (posedge clk or posedge reset)
    begin
	if (reset == 1)
		q <= 0;
	else
		begin
			if (enable)	//同步使能
				q <= q + 1;	
			
			if (q[3:0] == 4'h9)
				begin
					q[3:0] <= 4'h0;	
					q[7:4] <= q[7:4] + 1;
				end
				
			if ((q[3:0] == 4'h9) && (q[7:4] == 4'h5))
				begin
					q[7:4] <= 4'h0;	
					q[3:0] <= 4'h0;	
					q[11:8] <= q[11:8] + 1;	
				end
				
			if ((q[3:0] == 4'h9) && (q[7:4] == 4'h5) && (q[11:8] == 4'h9))	
				begin
					q[11:8] <= 4'h0;	
					q[7:4] <= 4'h0;	
					q[3:0] <= 4'h0;
					q[15:12] <= q[15:12] + 1;	
				end
				
			if ((q[3:0] == 4'h9) && (q[7:4] == 4'h5) 
			     && (q[11:8] == 4'h9) && (q[15:12] == 4'h5))	
				q[15:12] <= 4'h0;			
		 end
	  end
   endmodule