module RLSifter_4(clk,reset,q);
       parameter WIDTH=4;
       input clk,reset;
       output [WIDTH-1:0] q;

       reg [WIDTH-1:0] q;

always@(posedge clk or posedge reset)
    begin
       if(reset==1)
         q<=1'b1;
       else 
         q<={q[WIDTH-2:0], q[WIDTH-1]};
    end
endmodule