module mux_4_1(datain,dataout,sel);
      input [3:0] sel;
      input [15:0] datain;
      output [15:0] dataout;

     reg [15:0] dataout;

 always @(sel)
      begin
      case (sel)
            4'b0001: dataout<=datain [3:0];
            4'b0010: dataout<=datain [7:4];
            4'b0100: dataout<=datain [11:8];
            4'b1000: dataout<=datain [15:12];
      endcase
      end

 endmodule