?? count_8.v
字號:
module count_8 (clk, reset, temp, q);
input clk, reset;
output temp;
output [7:0] q;
reg [7:0] q;
reg temp;
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
q <= 0;
temp <= 0;
end
else
begin
q = q + 1;
if (q == 8'h00)
temp <= ~temp;
end
end
endmodule
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