/*! \file prism2.c \brief Prism2 802.11b Wireless-LAN Interface Driver. */
//*****************************************************************************
//
// File Name	: 'prism2.c'
// Title		: Prism2 802.11b Wireless-LAN Interface Driver
// Author		: Pascal Stang
// Created		: 12/27/2004
// Revised		: 1/7/2005
// Version		: 0.1
// Target MCU	: Atmel AVR series
// Editor Tabs	: 4
//
// Description	: This driver provides initialization and transmit/receive
//		functions for the Prism2 802.11b Wireless-LAN Controller.
//
//*****************************************************************************

#include <avr/io.h>
#include <avr/interrupt.h>
#include <string.h>

#include "global.h"
#include "timer.h"
#include "rprintf.h"
#include "debug.h"

#include "net.h"
#include "prism2.h"

// include configuration
#include "prism2conf.h"

u16 TxHeader[34];
void nicInit(void)
{
	prism2Init();
}

void nicSend(unsigned int len, unsigned char* packet)
{
	u16 i;
	u16 txfid;
	u08 stat;
	// request free buffer space to store outgoing frame
	prism2Command(PRISM2_CMD_ALLOC, len+44+14+6);
	// wait for buffer to be allocated
	while( !(prism2Read16(PRISM2_REG_EVSTAT) & PRISM2_EVENT_ALLOC) );
	// get the buffer FID
	txfid = prism2Read16(PRISM2_REG_ALLOCFID);
	// ACK the alloc event
	prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_ALLOC);

//	rprintf("PRISM2: TxFID=0x");
//	rprintfu16(txfid);
//	rprintfCRLF();

	// adjust packet length because MAC addresses and type
	// will be written seperately from packet payload
	len-=14;

	// write the outgoing frame to BAP
	// begin with control structure
	prism2SetupTxHeader(TxHeader);
	
	// write dest and src MAC addresses
	for(i=0;i<6;++i)
		TxHeader[23+i] = packet[i*2+1]<<8 | packet[i*2];
	// write length
	TxHeader[29] = htons(len+8);
	// write type
	TxHeader[33] = packet[13]<<8 | packet[12];

//	debugPrintHexTable(34*2, (u08*)TxHeader);
//	rprintfCRLF();
//	debugPrintHexTable(len, &packet[14]);

	// write Tx header out to BAP
	prism2WriteBAP0(txfid, 0, TxHeader, 34);
	// write packet out to BAP
	prism2WriteBAP0(txfid, 68, (u16*)&packet[14], (len+1)>>1);
	// issue transmit command	
	stat = prism2Command(PRISM2_CMD_TX, txfid);
	if(stat)
		rprintf("Transmit failed: 0x%x\r\n", stat);
	// do cleanup
	prism2EventCheck();
}

void nicGetMacAddress(u08* macaddr)
{
	prism2GetMacAddress(macaddr);
}

void nicSetMacAddress(u08* macaddr)
{
	// not yet supported
}

void nicRegDump(void)
{
	prism2CardRegDump();
	prism2RegDump();
}

void prism2SetupTxHeader(u16* header)
{
	u16 i;
    
	// clear out header
	for(i=0;i<22;i++)
		header[i] = 0x00;

	// set TxRate and retry count
	header[5] = (0<<8) | 0;
	// 0x00 = automatic selection
	// 0x0A = 10  = 1.0Mbit/s
	// 0x14 = 20  = 2.0Mbit/s
	// 0x37 = 55  = 5.5Mbit/s
	// 0x6E = 110 = 11 Mbit/s

	// set TxControl
	header[6] = 0x0004;

	// write length
	// (not really needed since card will pull info from 802.3 header)
	//TxHeader[22] = len+8;

	// fill in 802.3 header fields
	TxHeader[30] = 0xAAAA;
	TxHeader[31] = 0x0003;
	TxHeader[32] = 0x0000;

	// src mac address @ byte offset 52
}

void prism2EventCheck(void)
{
	unsigned int evstat_data;

	evstat_data = prism2Read16(PRISM2_REG_EVSTAT);
	
	if(evstat_data & PRISM2_EVENT_TX)
	{
		prism2Write16(PRISM2_REG_EVACK,PRISM2_EVENT_TX);
	}

	if(evstat_data & PRISM2_EVENT_TXEXEC)
	{
		prism2Write16(PRISM2_REG_EVACK,PRISM2_EVENT_TXEXEC);
	}

	if(evstat_data & PRISM2_EVENT_ALLOC)
	{
		prism2Write16(PRISM2_REG_EVACK, 0x0002);
	}

	if(evstat_data & PRISM2_EVENT_CMD)
	{
		prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_CMD);
	}

	if(evstat_data & PRISM2_EVENT_INFO)
	{
		prism2Read16(PRISM2_REG_INFOFID);
		prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_INFO);
	}

	if(evstat_data & PRISM2_EVENT_INFDROP)
	{
		prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_INFDROP);
	}

	if(evstat_data & PRISM2_EVENT_WTERR)
	{
		prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_WTERR);
	}
}


unsigned int nicPoll(unsigned int maxlen, unsigned char* packet)
{
	u16 rxfid=0;
	u16 packetLength=0;

	// check if packets have been received
	if(prism2Read16(PRISM2_REG_EVSTAT) & PRISM2_EVENT_RX)
	{
		// we have a receive event
		// get RxFID
		rxfid = prism2Read16(PRISM2_REG_RXFID);
		// read the packet length
		prism2ReadBAP0(rxfid, 44, &packetLength, 1);
	}

	// if there's no packet or an error - exit
	if( !packetLength )
		return 0;
	
	// drop anything too big for the buffer
	if( packetLength > maxlen )
	{
		// ACK the receive event to finish up
		prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_RX);
		return 0;
	}

	// packet is available, retrieve data
	// this is a hack: while reading in data,
	// convert 802.2/3 header to ethernet header
	// first get dest and src MAC addresses
	prism2ReadBAP0(rxfid, 46, (u16*)&packet[0], 6);
	// skip length, snap, and ctrl fields
	// begin data copy again at type field
	prism2ReadBAP0(rxfid, 46+12+8, (u16*)&packet[12], packetLength-6);
	// ACK the receive event to finish up
	prism2Write16(PRISM2_REG_EVACK, PRISM2_EVENT_RX);

	return packetLength;
}

void prism2InitPorts(void)
{
#if NIC_CONNECTION == MEMORY_MAPPED
  	// enable external SRAM interface - no wait states
  	sbi(MCUSR, SRE);
#else
	// set address port to output
	outb(PRISM2_ADDRESS_DDR, PRISM2_ADDRESS_MASK);
	outb(PRISM2_HADDRESS_DDR, PRISM2_HADDRESS_MASK);
    
	// set data port to input with pull-ups
	outb(PRISM2_DATA_DDR, 0x00);
	outb(PRISM2_DATA_PORT, 0xFF);

	// initialize the control port read and write pins to de-asserted
	sbi( PRISM2_CONTROL_PORT, PRISM2_CONTROL_IORD );
	sbi( PRISM2_CONTROL_PORT, PRISM2_CONTROL_IOWR );
	sbi( PRISM2_CONTROL_PORT, PRISM2_CONTROL_MEMRD );
	sbi( PRISM2_CONTROL_PORT, PRISM2_CONTROL_MEMWR );
	// set the read and write pins to output
	sbi( PRISM2_CONTROL_DDR, PRISM2_CONTROL_IORD );
	sbi( PRISM2_CONTROL_DDR, PRISM2_CONTROL_IOWR );
	sbi( PRISM2_CONTROL_DDR, PRISM2_CONTROL_MEMRD );
	sbi( PRISM2_CONTROL_DDR, PRISM2_CONTROL_MEMWR );
#endif
	// set reset pin to output
	sbi( PRISM2_RESET_DDR, PRISM2_RESET_PIN );

	// clear -REG pin
	sbi(DDRB, 6);
	cbi(PORTB, 6);
	// setup IREQ pin
	cbi(DDRB, 7);
	sbi(PORTB, 7);
}
void prism2Init(void){
	u08 result;
	u16 buffer[20];

//	rprintf("Init ports\r\n");
	prism2InitPorts();

	// assert hardware reset
	sbi( PRISM2_RESET_PORT, PRISM2_RESET_PIN );
	// wait
	delay_ms(10);
	// release hardware reset
	cbi( PRISM2_RESET_PORT, PRISM2_RESET_PIN );
	delay_ms(100);

/*
	// soft-reset card
	prism2WriteMem(0x3E0+PCMCIA_ATTR_COR, 0x80);
	delay_ms(10);
	prism2WriteMem(0x3E0+PCMCIA_ATTR_COR, 0x00);
	// wait until soft-reset is done
	delay_ms(500);

	// set 8-bit PCMCIA I/O mode
	prism2WriteMem(0x3E0+PCMCIA_ATTR_CSR, 0x20);

	prism2WriteMem(0x3E0+PCMCIA_ATTR_CSR, 0x04);
	timerPause(1000);
	prism2WriteMem(0x3E0+PCMCIA_ATTR_CSR, 0x00);
*/
	// enable PCMCIA I/O mode
	prism2WriteMem(0x3E0+PCMCIA_ATTR_COR, prism2ReadMem(0x3E0+PCMCIA_ATTR_COR) | 0x01);
//	prism2CardRegDump();

	rprintf("Prism2 Initializing...\r\n");
	if( (result = prism2Command(PRISM2_CMD_INIT,0)) )
	{
		rprintf("Prism2 Initialization Failure\r\n");
		rprintf("Result Code = %x\r\n",result);
	}
	
	rprintf("Prism2 Initialized\r\n");

	// set SSID
	prism2SetSSID("airdrop");

	// set max packet size
	buffer[0] = 0x0002;
	buffer[1] = PRISM2_RID_CNFMAXDATALEN;
	buffer[2] = 0x05DC;
	prism2WriteRID(PRISM2_RID_CNFMAXDATALEN, 0, buffer, 3);

	// set operating mode / port type
	buffer[0] = 0x0002;
	buffer[1] = PRISM2_RID_CNFPORTTYPE;
	//buffer[2] = 0x0000; // IBSS
	buffer[2] = 0x0001; // BSS
	prism2WriteRID(PRISM2_RID_CNFPORTTYPE, 0, buffer, 3);

	// set channel
//	buffer[0] = 0x0002;
//	buffer[1] = 0xFC03;
//	buffer[2] = 0x0001;
//	prism2WriteRID(0xFC00, 0, buffer, 3);

	// enable the interface
	prism2Command(PRISM2_CMD_ENABLE_MAC0,0);
}