?? lpc23xx.h
字號(hào):
#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
#define UART2_BASE_ADDR 0xE0078000
#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))
#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))
#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))
#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))
#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))
#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))
/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
#define UART3_BASE_ADDR 0xE007C000
#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))
#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))
#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))
#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))
#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))
#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))
#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))
/* I2C Interface */
#define I2C_BASE_ADDR 0xE001C000
#define I2CONSET (*(volatile unsigned long *)(I2C_BASE_ADDR + 0x00))
#define I2STAT (*(volatile unsigned long *)(I2C_BASE_ADDR + 0x04))
#define I2DAT (*(volatile unsigned long *)(I2C_BASE_ADDR + 0x08))
#define I2ADR (*(volatile unsigned long *)(I2C_BASE_ADDR + 0x0C))
#define I2SCLH (*(volatile unsigned long *)(I2C_BASE_ADDR + 0x10))
#define I2SCLL (*(volatile unsigned long *)(I2C_BASE_ADDR + 0x14))
#define I2CONCLR (*(volatile unsigned long *)(I2C_BASE_ADDR + 0x18))
/* I2C Interface 0 */
#define I2C0_BASE_ADDR 0xE001C000
#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
/* I2C Interface 1 */
#define I2C1_BASE_ADDR 0xE005C000
#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
/* I2C Interface 2 */
#define I2C2_BASE_ADDR 0xE0080000
#define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))
#define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))
#define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))
#define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))
#define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))
#define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))
#define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))
/* SPI0 (Serial Peripheral Interface 0) */
#define SPI0_BASE_ADDR 0xE0020000
#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
/* SSP0 Controller */
#define SSP0_BASE_ADDR 0xE0068000
#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))
#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))
#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))
#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))
#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))
#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))
#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))
#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))
#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))
#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))
/* SSP1 Controller */
#define SSP1_BASE_ADDR 0xE0030000
#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))
#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))
#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))
#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))
#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))
#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))
#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))
#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))
#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))
#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))
/* Real Time Clock */
#define RTC_BASE_ADDR 0xE0024000
#define ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
#define CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
#define CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
#define CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
#define AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
#define CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
#define CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
#define CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
#define SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
#define MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
#define HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
#define DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
#define DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
#define DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
#define MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
#define YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
#define CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))
#define ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
#define ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
#define ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
#define ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
#define ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
#define ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
#define ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
#define ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
#define PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))
#define PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
/* A/D Converter 0 (AD0) */
#define AD0_BASE_ADDR 0xE0034000
#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
#define ADDR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
#define ADDR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
#define ADDR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
#define ADDR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
#define ADDR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
#define ADDR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
#define ADDR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
#define ADDR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
/* D/A Converter */
#define DAC_BASE_ADDR 0xE006C000
#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
/* Watchdog */
#define WDG_BASE_ADDR 0xE0000000
#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
#define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10))
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
#define CAN_ACCEPT_BASE_ADDR 0xE003C000
#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))
#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))
#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))
#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))
#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))
#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
#define CAN_CENTRAL_BASE_ADDR 0xE0040000
#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))
#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))
#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
#define CAN1_BASE_ADDR 0xE0044000
#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))
#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))
#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))
#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))
#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))
#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))
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