?? startup.s.orig
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
INCLUDE kxarm.h
INCLUDE armmacros.s
INCLUDE s3c2410x.inc
;-------------------------------------------------------------------------------
MemoryMap EQU 0x2a4
BANK_SIZE EQU 0x00100000 ; 1MB per bank in MemoryMap array
BANK_SHIFT EQU 20
; Define RAM space for the Page Tables:
;
PHYBASE EQU 0x30000000 ; physical start
PTs EQU 0x30010000 ; 1st level page table address (PHYBASE + 0x10000)
; save room for interrupt vectors.
;-------------------------------------------------------------------------------
TEXTAREA
IMPORT main
; Set up the MMU and Dcache for bootloader.
;
; This routine will initialize the first-level page table based up the contents
; of the MemoryMap array and enable the MMU and caches.
;
; Copy the image to RAM if it's not already running there.
;
; Include Files
; Defines
;------------------------------------------------------------------------------
; BUGBUG - ?
PLLVAL EQU (((0xa1 << 12) + (0x3 << 4) + 0x1))
;------------------------------------------------------------------------------
; Cache Configuration
DCACHE_LINES_PER_SET_BITS EQU (6)
DCACHE_LINES_PER_SET EQU (64)
DCACHE_NUM_SETS EQU (8)
DCACHE_SET_INDEX_BIT EQU (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE EQU (32)
;------------------------------------------------------------------------------
; Sleep state constants
;
; Location of sleep data
; BUGBUG - this needs to be declared as a local var.
SLEEPDATA_BASE_PHYSICAL EQU 0x30058000
; Sleep State memory locations
SleepState_Data_Start EQU (0)
SleepState_WakeAddr EQU (SleepState_Data_Start + 0)
SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE)
SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE)
SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE)
SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE)
SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE)
SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE)
SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE)
SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE)
SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE)
SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE)
SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE)
SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE)
SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE)
SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE)
SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE)
SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE)
SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE)
SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE)
SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE)
SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE)
SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE)
SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE)
SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE)
SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE)
SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE)
SLEEPDATA_SIZE EQU (SleepState_Data_End - SleepState_Data_Start) / 4
; External Variables
; External Functions
; Global Variables
; Local Variables
; Local Functions
;-------------------------------------------------------------------------------
; Function: Startup
;
; Main entry point for CPU initialization.
;
STARTUPTEXT
LEAF_ENTRY StartUp
; richard
; 1. config GPF 4~7 as o/p
ldr r1, = GPFCON
ldr r2, = 0x55aa
str r2, [r1]
// 2. light up GPF 4 (led d12 on board)
ldr r0, = GPFDAT
ldr r1, = 0xE0
str r1, [r0]
; end
; Jump over power-off code.
b ResetHandler
; Power-off the CPU.
str r1, [r0] ; enable SDRAM self-refresh.
str r3, [r2] ; MISCCR setting.
str r5, [r4] ; POWER OFF!!!!!
b .
ResetHandler
; Make sure that TLB & cache are consistent
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 ; flush both TLB
mcr p15, 0, r0, c7, c5, 0 ; invalidate instruction cache
mcr p15, 0, r0, c7, c6, 0 ; invalidate data cache
ldr r0, = GPFCON
ldr r1, = 0x55aa
str r1, [r0]
ldr r0, = WTCON ; disable watch dog
ldr r1, = 0x0
str r1, [r0]
ldr r0, = INTMSK
ldr r1, = 0xffffffff ; disable all interrupts
str r1, [r0]
ldr r0, = INTSUBMSK
ldr r1, = 0x7ff ; disable all sub interrupt
str r1, [r0]
ldr r0, = INTMOD
mov r1, #0x0 ; set all interrupt as IRQ
str r1, [r0]
ldr r0, = CLKDIVN
ldr r1, = 0x3 ; 0x0 = 1:1:1, 0x1 = 1:1:2
; 0x2 = 1:2:2, 0x3 = 1:2:4,
; 0x8 = 1:4:4
str r1, [r0]
ands r1, r1, #0x2 ; set AsyncBusMode
beq %F10
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF:OR:R1_iA
mcr p15, 0, r0, c1, c0, 0
10
ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
ldr r1, = 0xffffff
str r1, [r0]
ldr r0, = MPLLCON ; Configure MPLL
; Fin=12MHz, Fout=50MHz
ldr r1, = PLLVAL
str r1, [r0]
ldr r0, = UPLLCON ; Fin=12MHz, Fout=48MHz
ldr r1, = ((0x48 << 12) + (0x3 << 4) + 0x2)
str r1, [r0]
mov r0, #0x2000
20
subs r0, r0, #1
bne %B20
;------------------------------------------------------------------------------
; Add for Power Management
ldr r1, =GSTATUS2 ; Determine Booting Mode
ldr r10, [r1]
tst r10, #0x2
beq %F30 ; if not wakeup from PowerOffmode
; skip MISCCR setting
ldr r1, =MISCCR ; MISCCR's Bit 17, 18, 19 -> 0
ldr r0, [r1] ; I don't know why, Just fallow Sample Code.
bic r0, r0, #(7 << 17) ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
str r0, [r1]
30
;------------------------------------------------------------------------------
; Initialize memory controller
add r0, pc, #MEMCTRLTAB - (. + 8)
ldr r1, = BWSCON ; BWSCON Address
add r2, r0, #52 ; End address of MEMCTRLTAB
40 ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B40
;------------------------------------------------------------------------------
; Add for Power Management
tst r10, #0x2
beq BringUpWinCE ; Normal Mode Booting
;------------------------------------------------------------------------------
; Recover Process : Starting Point
;
; 1. Checksum Calculation saved Data
ldr r5, =SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep mode info data structure
mov r3, r5 ; pointer for checksum calculation
mov r2, #0
ldr r0, =SLEEPDATA_SIZE ; get size of data structure to do checksum on
50 ldr r1, [r3], #4 ; pointer to SLEEPDATA
and r1, r1, #0x1
mov r1, r1, LSL #31
orr r1, r1, r1, LSR #1
add r2, r2, r1
subs r0, r0, #1 ; dec the count
bne %b50 ; loop till done
ldr r0,=GSTATUS3
ldr r3, [r0] ; get the Sleep data checksum from the Power Manager Scratch pad register
teq r2, r3 ; compare to what we saved before going to sleep
bne BringUpWinCE ; bad news - do a cold boot
; 2. MMU Enable
ldr r10, [r5, #SleepState_MMUDOMAIN] ; load the MMU domain access info
ldr r9, [r5, #SleepState_MMUTTB] ; load the MMU TTB info
ldr r8, [r5, #SleepState_MMUCTL] ; load the MMU control info
ldr r7, [r5, #SleepState_WakeAddr ] ; load the LR address
nop
nop
nop
nop
nop
; if software reset
mov r1, #0
teq r1, r7
bne %f60
bl BringUpWinCE
; wakeup routine
60 mcr p15, 0, r10, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r9, c2, c0, 0 ; PT address
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mcr p15, 0, r8, c1, c0, 0 ; restore MMU control
; 3. Jump to Kernel Image's fw.s (Awake_address)
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