module rcvr (data_out,received,s_in,clock,reset);
input  s_in,clock,reset;
output [7:0]  data_out;
output  received;
parameter band_cnt=16;//代表波特率輸入數(shù)據(jù),數(shù)字代表接收時鐘的分頻數(shù)
reg s_in1,s_in2,rxclk_enable,received;
reg [3:0] clkdiv,control_cnt,clken;
reg [7:0] rsr,rbr;
reg  rxclk,read_strobe;//rxclk接收時鐘
/*輸入數(shù)據(jù)寄存器,用于下降沿檢測*/
always @ (posedge clock)
       begin  s_in1<=s_in;  s_in2<=s_in1;  end
/*接收時鐘使能,在時鐘使能范圍內(nèi)產(chǎn)生接收時鐘并對輸入數(shù)據(jù)采樣*/
always @ (posedge clock or posedge reset)
        begin  if (reset)   clken<=1'b0; 
              else  begin
                           if ( s_in==0) 
                               begin if(clken>8)  clken<=1'b0;  
                                     else        clken=clken+1;
                               end
                           else clken<=1'b0; 
                      end
        end
always @ (posedge clock or posedge reset)
       begin  if (reset)   rxclk_enable<=1'b0;                    
              else if (clken==8)   
                     begin  rxclk_enable<=1'b1;  end                            
              else if  (control_cnt==10)
                    rxclk_enable<=1'b0;
       end
/*控制計數(shù)器*/
always @ (posedge rxclk or posedge reset or negedge rxclk_enable)  
       begin if (reset)        control_cnt<=0;
             else  begin if (!rxclk_enable)   control_cnt<=0;
                         else         control_cnt<= control_cnt+1;
                   end
       end
/*是否工作標志,1為工作,0為空閑*/
always @ (posedge clock or posedge reset ) 
       begin if (reset) received<=1'b0;
             //else if ((control_cnt>=1 && control_cnt<=9) )
                     // received<=1'b1;
             else   begin  //(control_cnt==11) 
                        received<=rxclk_enable;
                        read_strobe<=rxclk_enable;
                    end
       end
/*產(chǎn)生接收時鐘*/
always @ (posedge clock or posedge reset ) 
       begin  if (reset) clkdiv<=0;
              else  begin  
                         if  (rxclk_enable)
                             begin if (clkdiv>=(band_cnt-1)) clkdiv<=0;
                                   else clkdiv<=clkdiv+1;
                             end
                    end
       end
/*接收數(shù)據(jù)進程: 
               rsr: receiver  serial  register :接收移位寄存器. 
               rbr: receiver  buffer  register  接收緩沖寄存器*/
always @ (posedge clock or posedge reset )
       begin  if (reset) rxclk<=0;
              else if(clkdiv>=band_cnt-1) rxclk<=1;
                   else rxclk<=0;
       end
   //assign rxclk=(clkdiv>=band_cnt-1)?1:0;
always @ (posedge rxclk or posedge reset )  
            if (reset)       
                      begin rsr<=8'b0;
                            rbr<=8'b0;
                           // framing_error<=1'b0;
                      end
             else     begin  if (control_cnt>=0 && control_cnt<=7)
                                begin  rsr[7]<=s_in2;
                                       rsr[6:0]<= rsr[7:1];
                                end
                             else if (control_cnt==8)
                                    rbr<=rsr;  
                            // else if ( (control_cnt==9)&&(s_in2!==1'b0) )
                                  //   framing_error<=1'b1;
                             //else    framing_error<=1'b0;
                      end
/*always @ (posedge rxclk or posedge reset ) 
      begin  if (reset) data_out=0;
              else if(rxclk_enable)  data_out<=rsr;
                   else data_out=8'bz;
       end*/
       assign data_out= ! read_strobe ? rsr : 8'bz;//并行數(shù)據(jù)輸出
endmodule