?? 2410init.s
字號:
@ b G5
ldr r5, =NFCONF @DsNandFlash
ldr r0, [r5]
and r0, r0, #~0x8000 @可以通過寫nfconf寄存器的第15位或者11位進行使能或者禁止
str r0, [r5]
ldr pc, =copy_proc_beg
#===========================================================
copy_proc_beg: @不是已經從nandflash搬運過程序嗎？為啥還要初始化這些ro，ri，bss等段？
adr r0, ResetEntry @這樣豈不是把已經搬運過來的程序給沖掉了？
@ b copy_proc_beg
ldr r2, BaseOfROM
cmp r0, r1 @怎么要和r1比較？
ldreq r0, TopOfROM
beq InitRam
ldr r3, TopOfROM
H0:
ldmia r0!, {r4-r7}
stmia r2!, {r4-r7}
cmp r2, r3
bcc H0
sub r2, r2, r3
sub r0, r0, r2
InitRam: @初始化bss和zi
ldr r2, BaseOfBSS
ldr r3, BaseOfZero
I0:
cmp r2, r3
ldrcc r1, [r0], #4
strcc r1, [r2], #4
bcc I0
mov r0, #0
ldr r3, EndOfBSS
I1:
cmp r2, r3
strcc r0, [r2], #4
bcc I1
#;send reset status to main function
ldr r1, =GSTATUS2
ldr r0, [r1]
str r0, [r1] @clear reset status
.ifndef THUMBCODE
@ bl Main @ Don't use main() because ......
@ b .
ldr r8,=Main
mov pc , r8
.endif
.ifdef THUMBCODE @ for start-up code for Thumb mode
orr lr,pc,#1
bx lr
.thumb
bl Main @ Don't use main() because ......
b .
.arm
.endif
#===========================================================
.extern disable_irq
disable_irq:
mrs r0, cpsr @enter svc mode and disable irq,fiq
orr r0, r0, #0xc0
msr cpsr_c, r0
mov pc, lr
ReadNandID:
ldr r7,=NFCONF
ldr r0,[r7,#0] @NFChipEn();
bic r0,r0,#0x800
str r0,[r7,#0]
mov r0,#0x90 @WrNFCmd(RdIDCMD);
strb r0,[r7,#4]
mov r4,#0 @WrNFAddr(0);
strb r4,[r7,#8]
J1: @while(NFIsBusy());
ldr r0,[r7,#0x10]
tst r0,#1
beq J1
ldrb r0,[r7,#0xc] @id = RdNFDat()<<8;
mov r0,r0,lsl #8
ldrb r1,[r7,#0xc] @id |= RdNFDat();
orr r5,r1,r0
ldr r0,[r7,#0] @NFChipDs();
orr r0,r0,#0x800
str r0,[r7,#0]
mov pc,lr
ReadNandStatus:
ldr r7,=NFCONF
ldr r0,[r7,#0] @NFChipEn();
bic r0,r0,#0x800
str r0,[r7,#0]
mov r0,#0x70 @WrNFCmd(QUERYCMD);
strb r0,[r7,#4]
ldrb r1,[r7,#0xc] @r1 = RdNFDat();
ldr r0,[r7,#0] @NFChipDs();
orr r0,r0,#0x800
str r0,[r7,#0]
mov pc,lr
WaitNandBusy:
mov r0,#0x70 @WrNFCmd(QUERYCMD);
ldr r1,=NFCONF
strb r0,[r1,#4]
K1: @while(!(RdNFDat()&0x40));
ldrb r0,[r1,#0xc]
tst r0,#0x40
beq K1
mov r0,#0 @WrNFCmd(READCMD0);
strb r0,[r1,#4]
mov pc,lr
CheckBadBlk:
mov r7, lr
ldr r5, =NFCONF
bic r0, r0, #0x1f @addr &= ~0x1f;
ldr r1,[r5,#0] @NFChipEn()
bic r1,r1,#0x800
str r1,[r5,#0]
mov r1,#0x50 @WrNFCmd(READCMD2)
strb r1,[r5,#4]
mov r1, #5
strb r1,[r5,#8] @WrNFAddr(5)
strb r0,[r5,#8] @WrNFAddr(addr)
mov r1,r0,lsr #8 @WrNFAddr(addr>>8)
strb r1,[r5,#8]
cmp r6,#0 @if(NandAddr)
movne r0,r0,lsr #16 @WrNFAddr(addr>>16)@什么指令
strneb r0,[r5,#8] @什么指令
bl WaitNandBusy @WaitNFBusy()
ldrb r0, [r5,#0xc] @RdNFDat()
sub r0, r0, #0xff
mov r1,#0 @WrNFCmd(READCMD0)
strb r1,[r5,#4]
ldr r1,[r5,#0] @NFChipDs()
orr r1,r1,#0x800
str r1,[r5,#0]
mov pc, r7
ReadNandPage:
mov r7,lr
mov r4,r1
ldr r5,=NFCONF
ldr r1,[r5,#0] @NFChipEn()
bic r1,r1,#0x800
str r1,[r5,#0]
mov r1,#0 @WrNFCmd(READCMD0)
strb r1,[r5,#4]
strb r1,[r5,#8] @WrNFAddr(0)
strb r0,[r5,#8] @WrNFAddr(addr)
mov r1,r0,lsr #8 @WrNFAddr(addr>>8)
strb r1,[r5,#8]
cmp r6,#0 @if(NandAddr)
movne r0,r0,lsr #16 @WrNFAddr(addr>>16)
strneb r0,[r5,#8]
ldr r0,[r5,#0] @InitEcc()
orr r0,r0,#0x1000
str r0,[r5,#0]
bl WaitNandBusy @WaitNFBusy()
mov r0,#0 @for(i=0; i<512; i++)
L1:
/* ldrb r1,[r5,#0xc] @buf[i] = RdNFDat()
nop
nop
nop
nop
ldrb r2,[r5,#0xc] @buf[i] = RdNFDat()
add r1,r1,r2,lsl #8
nop
nop
nop
nop
ldrb r2,[r5,#0xc] @buf[i] = RdNFDat()
add r1,r1,r2,lsl #16
nop
nop
nop
nop
ldrb r2,[r5,#0xc] @buf[i] = RdNFDat()
add r1,r1,r2,lsl #24
str r1,[r4,r0]
add r0,r0,#4
nop
nop
nop
nop*/
ldrb r1,[r5,#0xc] @buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
ldrb r1,[r5,#0xc] @buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
ldrb r1,[r5,#0xc] @buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
ldrb r1,[r5,#0xc] @buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
@ bic r0,r0,#0x10000 @這句搞什么飛機？
cmp r0,#0x200
bcc L1
ldr r0,[r5,#0] @NFChipDs()
orr r0,r0,#0x800
str r0,[r5,#0]
mov pc,r7
#===========================================================
#function initializing stacks
InitStacks:
#Don't use DRAM,such as stmfd,ldmfd......
#SVCstack is initialized before
#Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 @UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 @AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 @IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 @FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 @SVCMode
ldr sp,=SVCStack
#USER mode has not be initialized.
mov pc,lr
#The LR register won't be valid if the current mode is not SVC mode.
.LTORG
SMRDATA:
# Memory configuration should be optimized for best performance
# The following parameter is not optimized.
# Memory access cycle parameter strategy
# 1) The memory settings is safe parameters even at HCLK=75Mhz.
# 2) SDRAM refresh period is for HCLK=75Mhz.
@ .long (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
@ .long 0x02000000
.long (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) @GCS0
.long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) @GCS1
.long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) @GCS2
.long 0x1f7c@((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
.long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) @GCS4
.long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) @GCS5
@ .long ((B6_MT<<15)+(3<<13)+(5<<8)+(3<<4)+(B6_Trcd<<2)) @((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) @GCS6
.long 0x0001e538
.long ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) @((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) @GCS7
@ .long ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
.long 0x00ac01e9
.long 0x07 @SCLK power saving mode, BANKSIZE 128M/128M
.long 0x30 @MRSR6 CL=3clk
.long 0x30 @MRSR7
# DCD 0x20 @MRSR6 CL=2clk
# DCD 0x20 @MRSR7
BaseOfROM: .long Image_RO_Base
TopOfROM: .long Image_RO_Limit
BaseOfBSS: .long Image_RW_Base
BaseOfZero: .long Image_ZI_Base
EndOfBSS: .long Image_ZI_Limit
.ifndef THUMBCODE
ldr r8,=Main
mov pc , r8
@ bl Main @ Don't use main() because ......
@ b .
.endif
.ifdef THUMBCODE @ for start-up code for Thumb mode
orr lr,pc,#1
bx lr
.thumb
bl Main @ Don't use main() because ......
b .
.arm
.endif
/* GBLS main_entry
MainEntry: .ascii "Main"
.extern main_entry
GotoMain: .long main_entry */
.ALIGN
.equ HandleReset, _ISR_STARTADDRESS
.equ HandleUndef, _ISR_STARTADDRESS+4
.equ HandleSWI, _ISR_STARTADDRESS+4*2
.equ HandlePabort, _ISR_STARTADDRESS+4*3
.equ HandleDabort, _ISR_STARTADDRESS+4*4
.equ HandleReserved, _ISR_STARTADDRESS+4*5
.equ HandleIRQ, _ISR_STARTADDRESS+4*6
.equ HandleFIQ, _ISR_STARTADDRESS+4*7
#Don't use the label 'IntVectorTable',
#The value of IntVectorTable is different with the address you think it may be.
#IntVectorTable
.equ HandleEINT0, _ISR_STARTADDRESS+4*8
.equ HandleEINT1, _ISR_STARTADDRESS+4*9
.equ HandleEINT2, _ISR_STARTADDRESS+4*10
.equ HandleEINT3 , _ISR_STARTADDRESS+4*11
.equ HandleEINT4_7 , _ISR_STARTADDRESS+4*12
.equ HandleEINT8_23, _ISR_STARTADDRESS+4*13
.equ HandleRSV6 ,_ISR_STARTADDRESS+4*14
.equ HandleBATFLT ,_ISR_STARTADDRESS+4*15
.equ HandleTICK ,_ISR_STARTADDRESS+4*16
.equ HandleWDT ,_ISR_STARTADDRESS+4*17
.equ HandleTIMER0 ,_ISR_STARTADDRESS+4*18
.equ HandleTIMER1 ,_ISR_STARTADDRESS+4*19
.equ HandleTIMER2, _ISR_STARTADDRESS+4*20
.equ HandleTIMER3, _ISR_STARTADDRESS+4*21
.equ HandleTIMER4, _ISR_STARTADDRESS+4*22
.equ HandleUART2 , _ISR_STARTADDRESS+4*23
.equ HandleLCD ,_ISR_STARTADDRESS+4*24
.equ HandleDMA0 ,_ISR_STARTADDRESS+4*25
.equ HandleDMA1, _ISR_STARTADDRESS+4*26
.equ HandleDMA2, _ISR_STARTADDRESS+4*27
.equ HandleDMA3, _ISR_STARTADDRESS+4*28
.equ HandleMMC ,_ISR_STARTADDRESS+4*29
.equ HandleSPI0, _ISR_STARTADDRESS+4*30
.equ HandleUART1, _ISR_STARTADDRESS+4*31
.equ HandleRSV24, _ISR_STARTADDRESS+4*32
.equ HandleUSBD ,_ISR_STARTADDRESS+4*33
.equ HandleUSBH , _ISR_STARTADDRESS+4*34
.equ HandleIIC , _ISR_STARTADDRESS+4*35
.equ HandleUART , _ISR_STARTADDRESS+4*36
.equ HandleSPI1 , _ISR_STARTADDRESS+4*37
.equ HandleRTC, _ISR_STARTADDRESS+4*38
.equ HandleADC, _ISR_STARTADDRESS+4*39
.END
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